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CWDSP1650 dsp core order number c14049 technical manual january 1998
ii document db14-000071-00, first edition (january 1998) this document describes revision a of lsi logic corporations CWDSP1650 dsp core technical manual and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, call us at 1.800.574.4286 (u.s. and canada); +32.11.300.531 (europe); 408.433.7700 (outside u.s., canada, and europe) and ask for department jds; or visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1997, 1998 by lsi logic corporation. all rights reserved. trademark acknowledgment lsi logic logo design and coreware are registered trademarks and minirisc, gigablaze, g10, and right-first-time are trademarks of lsi logic corporation. pinedspcore and oakdspcore are registered trademarks of the dsp group. all other brand and product names may be trademarks of their respective companies.
contents iii contents preface chapter 1 introduction 1.1 core overview 1-1 1.2 features summary 1-3 1.2.1 general architecture 1-3 1.2.2 memory organization 1-4 1.2.3 physical technology 1-4 1.2.4 instruction set summary 1-4 1.3 coreware program 1-6 chapter 2 functional description 2.1 overview 2-1 2.1.1 CWDSP1650 core components 2-2 2.1.2 CWDSP1650 external modules 2-3 2.1.3 pipeline architecture 2-4 2.2 buses 2-5 2.2.1 data buses 2-5 2.2.2 address buses 2-5 2.3 program control unit (pcu) 2-6 2.3.1 interrupt handling in the pcu 2-8 2.4 computation and bit-manipulation unit (cbu) 2-8 2.4.1 computation unit 2-8 2.4.2 bit-manipulation unit (bmu) 2-12 2.4.3 saturation unit 2-15 2.5 data address arithmetic unit (daau) 2-17 2.5.1 daau registers 2-18 2.5.2 addressing modes 2-19 2.6 interrupt control unit (icu) 2-23
iv contents chapter 3 data formats, memory and addressing 3.1 data formats 3-1 3.2 program memory 3-4 3.2.1 program memory addressing modes 3-5 3.3 data memory 3-5 3.3.1 data memory addressing modes 3-6 chapter 4 registers 4.1 cbu registers 4-2 4.1.1 ax and bx accumulators 4-2 4.1.2 x, y, and p registers 4-6 4.1.3 interrupt context switching registers 4-7 4.1.4 shift value register 4-9 4.2 daau registers 4-9 4.2.1 address registers (r0-r5) 4-10 4.2.2 con?guration registers 4-11 4.2.3 base register (rb) 4-11 4.2.4 stack pointer register (sp) 4-12 4.2.5 alternative bank registers 4-12 4.2.6 minimum/maximum pointer latching register (mixp) 4-13 4.3 pcu registers 4-13 4.3.1 data value match register 4-14 4.3.2 internal con?guration register (icr) 4-14 4.3.3 program and loop counters 4-15 4.4 status registers 4-16 4.4.1 status register 0 (st0) 4-16 4.4.2 status register 1 (st1) 4-18 4.4.3 status register 2 (st2) 4-19 4.5 user-de?ned registers 4-21 chapter 5 signals 5.1 logic symbol 5-1 5.2 bus interface 5-3 5.3 program control interface 5-3 5.4 off-core data memory interface 5-4
contents v 5.5 user-de?ned register interface 5-6 5.6 emulation and trace buffer interface 5-7 5.7 processor control interface 5-9 5.8 scanice control interface 5-10 5.9 clock control interface 5-11 chapter 6 operation 6.1 reset 6-1 6.2 boot procedure 6-2 6.3 interrupts 6-3 6.3.1 maskable interrupts 6-4 6.3.2 nonmaskable interrupt (nmi) 6-6 6.3.3 trap/bi interrupts 6-6 6.3.4 interrupt protocol 6-7 6.3.5 interrupt priority 6-9 6.3.6 context switching 6-9 6.3.7 interrupt nesting 6-10 6.3.8 interruptible state 6-11 6.4 memory interface 6-12 6.4.1 memory interface with slow memory devices 6-14 6.5 user-de?ned register interface 6-15 6.6 program protection mechanism 6-16 6.7 clock control unit (ccu) 6-17 6.7.1 ccu operation 6-18 6.7.2 ccu register 6-19 chapter 7 instruction set 7.1 notations 7-1 7.1.1 register notations 7-1 7.1.2 number representation 7-3 7.1.3 data and program operands 7-3 7.1.4 option fields 7-5 7.1.5 condition field (cond) notations 7-5 7.1.6 flag notations 7-6 7.1.7 miscellaneous notations 7-6 7.2 conventions and general information 7-7 7.3 instruction functional groups 7-10
vi contents 7.3.1 shift operations 7-14 7.3.2 move and shift operations 7-15 7.3.3 rounding operations 7-16 7.3.4 division step operations 7-16 7.3.5 logical operations 7-16 7.3.6 max and min instructions 7-16 7.3.7 multiplication instructions 7-17 7.4 instruction set list 7-17 7.5 instruction opcode bit coding 7-203 chapter 8 on-chip emulation module (ocem) 8.1 ocem overview 8-1 8.1.1 breakpoint generation 8-1 8.1.2 program flow tracing 8-2 8.1.3 scanice debug support 8-2 8.1.4 suspended mode operation 8-3 8.2 ocem programming model 8-3 8.2.1 status 0 register 8-4 8.2.2 status 1 register 8-6 8.2.3 mode register 8-7 8.2.4 data address breakpoint register 8-9 8.2.5 data address mask register 8-9 8.2.6 program address breakpoint counters 8-10 8.2.7 program address breakpoint registers 8-10 8.2.8 program flow trace register and program flow trace buffer 8-10 8.3 ocem signals 8-14 8.3.1 service interface 8-16 8.3.2 boot logic interface 8-17 8.3.3 core memory bus interface 8-18 8.3.4 user-de?ned register interface 8-19 8.3.5 illegal access interface 8-19 8.3.6 core control interface 8-20 8.3.7 breakpoint interface 8-21 8.3.8 scanice interface 8-22 8.3.9 clocking and miscellaneous ocem signals 8-23 8.4 ocem breakpoints 8-24 8.4.1 program address breakpoint 8-24
contents vii 8.4.2 data address breakpoint 8-26 8.4.3 data value breakpoint 8-26 8.4.4 combined data address and data value breakpoints 8-27 8.4.5 external register breakpoint 8-27 8.4.6 abort breakpoint 8-27 8.4.7 illegal access breakpoint 8-28 8.4.8 branch and block repeat breakpoints 8-28 8.4.9 interrupt breakpoint 8-29 8.4.10 single-step operation 8-29 8.4.11 program flow trace buffer full breakpoint 8-29 chapter 9 scanice 9.1 scanice power saving registers 9-2 9.2 scanice requirements 9-4 9.3 scanice interface 9-6 9.3.1 scan control register 9-7 9.3.2 scanice control 9-9 9.3.3 external scan logic control 9-11 9.3.4 clock gating 9-12 9.4 CWDSP1650 scanice support 9-12 9.4.1 ocem scanice support 9-12 9.4.2 ccu scanice support 9-12 9.5 memory access during scanice 9-13 9.6 scanice reset 9-15 chapter 10 speci?cations 10.1 physical speci?cations 10-1 10.2 ac timing diagrams 10-1 10.2.1 ocem registers 10-2 10.2.2 data and program memory 10-4 10.2.3 user-de?ned registers 10-9 appendix a CWDSP1650 register summary customer feedback
viii contents figures 1.1 CWDSP1650 block diagram 1-2 2.1 CWDSP1650 block diagram 2-2 2.2 CWDSP1650 instruction pipeline 2-4 2.3 program control unit diagram 2-6 2.4 cu block diagram 2-9 2.5 bmu block diagram 2-13 2.6 data address arithmetic unit (daau) 2-17 2.7 interrupt control unit 2-23 3.1 signed and unsigned integer formats 3-2 3.2 program memory map 3-4 4.1 CWDSP1650 registers 4-1 4.2 p register 4-7 4.3 st0 and shadow registers 4-8 4.4 st1 and shadow registers 4-8 4.5 st2 and shadow registers 4-9 4.6 cfgi con?guration register 4-11 4.7 cfgj con?guration register 4-11 4.8 internal con?guration register (icr) 4-14 4.9 status register 0 (st0) 4-16 4.10 status register 1 (st1) 4-18 4.11 status register 2 (st2) 4-19 5.1 CWDSP1650 logic symbol 5-2 6.1 reset operation 6-2 6.2 entering boot mode 6-3 6.3 interrupt protocol 6-7 6.4 memory protection mechanism 6-17 6.5 ccu register 6-19 7.1 arithmetic shift right 7-15 7.2 logical shift right 7-15 7.3 arithmetic and logical shift left 7-15 8.1 status 0 register 8-4 8.2 status 1 register 8-6 8.3 mode register 8-7 8.4 program flow trace with corresponding trace buffer entries 8-13 9.1 power saving register with scan inserted 9-2
contents ix 9.2 scanice support in a CWDSP1650 system 9-5 9.3 example scan interface 9-7 9.4 scan control register 9-8 9.5 entry to scan using a breakpoint interrupt 9-10 9.6 stop scan mode 9-11 9.7 example scanice memory access scheme 9-14 10.1 writing the ocem 10-2 10.2 reading the ocem 10-3 10.3 data memory write access 10-4 10.4 data memory read access 10-5 10.5 program memory write access 10-5 10.6 program memory read access 10-6 10.7 memory access with wait state 10-7 10.8 user-de?ned register access 10-9 tables 1.1 CWDSP1650 instruction set summary 1-5 2.1 multiplier unit instructions 2-11 2.2 saturation over?ow 2-16 2.3 indirect addressing mode bits 2-20 3.1 signed and unsigned integer ranges 3-3 3.2 data memory address mapping 3-6 3.3 short direct addressing page values 3-7 4.1 cbu registers 4-2 4.2 ax and bx accumulator organization 4-3 4.3 ax accumulator loading values 4-4 4.4 bx accumulator loading values 4-5 4.5 daau registers 4-10 4.6 rn register grouping 4-10 4.7 validity of step and modulo in different addressing modes 4-11 4.8 alternative bank registers 4-13 4.9 pcu registers 4-13 4.10 status registers 4-16 6.1 maskable interrupt bits and signals 6-5 6.2 interrupts and priorities 6-9 6.3 interrupt latency after speci?c instructions 6-12 6.4 data memory space partitioning 6-13
x contents 6.5 memory signals interface 6-14 6.6 example for de?ning the number of wait cycles 6-15 6.7 user-de?ned register coding 6-16 6.8 ccu output clocks 6-18 7.1 register notations 7-1 7.2 program operand notation 7-3 7.3 data operand notation 7-4 7.4 option field notations 7-5 7.5 condition field notations 7-5 7.6 miscellaneous notations 7-6 7.7 CWDSP1650 instruction set listing 7-10 7.8 opcode i 7-203 7.9 opcode i or j 7-203 7.10 opcode ab 7-203 7.11 opcode abl 7-204 7.12 opcode rn 7-204 7.13 opcode rn* 7-204 7.14 opcode mod 7-205 7.15 opcode w 7-205 7.16 opcode reg/reg 7-205 7.17 opcode ii 7-206 7.18 opcode jj 7-206 7.19 opcode qq 7-207 7.20 opcode cond 7-207 7.21 opcode x 7-207 7.22 opcode bank in banke instructions 7-208 7.23 opcode ext 7-208 7.24 opcode bbbb 7-208 8.1 ocem programming model 8-3 8.2 ocem signal list 8-14 8.3 program address breakpoint components 8-25 9.1 scanice operational modes 9-3 9.2 six-pin scanice interface 9-6 10.1 CWDSP1650 physical layout size 10-1 10.2 ocem access timing constraints 10-3 10.3 memory interface timing constraints 10-7 10.4 user-de?ned register interface timing values 10-10 a.1 CWDSP1650 registers a-1
preface xi preface this book is the primary reference and technical manual for lsi logics CWDSP1650 dsp core. it contains a complete functional description for the core and includes both physical and electrical speci?cations. audience this document assumes that the reader has some familiarity with digital signal processors. the people who bene?t the most from this book are: engineers and managers who are evaluating the CWDSP1650 for possible use in a design engineers who are designing the CWDSP1650 into a chip engineers who are familiar with the cwdsp1640 can refer to the comparison of the cwdsp1640 and CWDSP1650 cores technical note for a full review of any design changes. organization this document has the following chapters and appendixes: chapter 1, introduction , discusses the CWDSP1650 in general, provides the cores key features, and discusses the coreware ? program. chapter 2, functional description , describes the purpose of each component block in the CWDSP1650. chapter 3, data formats, memory and addressing , describes the six supported data formats, the program and data memory spaces, and the addressing modes.
xii preface chapter 4, registers , de?nes the CWDSP1650 registers and describes the register bit ?elds. chapter 5, signals , describes the input, output, and bidirectional signals of the CWDSP1650 core. chapter 6, operation , describes the operation of the CWDSP1650 input/output interface. chapter 7, instruction set , provides a detailed description of the CWDSP1650 instruction set. chapter 8, on-chip emulation module (ocem) , describes the optional module that provides on-chip emulation for a CWDSP1650-based chip. chapter 9, scanice , describes the CWDSP1650 scanice components and describes an example scanice system design. chapter 10, speci?cations , contains the physical characteristics and ac timing for the CWDSP1650 core. appendix a, CWDSP1650 register summary , lists all of the CWDSP1650 registers and where a detailed description for each can be found. customer feedback , includes a form that you may use to fax us your comments about this document. related publications cwdsp1640 oakdspcore ? assembler and linker users guide , order no. c14029 cwdsp1640 oakdspcore ? c cross compiler users guide , order no. c14026.a cwdsp1640 oakdspcore ? debugger users guide , order no. c14027.a CWDSP1650 reference device users guide , available from lsi logic. CWDSP1650 evaluation kit users guide , order no. c14046 comparison of the cwdsp1640 and CWDSP1650 cores technical note , order no. c15030
preface xiii conventions used in this manual the ?rst time a word or phrase is de?ned in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x, for example, 0x32cf. binary numbers are indicated by the pre?x 0b, for example, 0b0011 0010 1100 1111.
xiv preface
1-1 chapter 1 introduction this chapter overviews lsi logics CWDSP1650 dsp core and contains the following sections: section 1.1, core overview section 1.2, features summary section 1.3, coreware program 1.1 core overview the CWDSP1650 is a 16-bit, ?xed-point digital signal processor (dsp) core designed for middle-end to high-end telecommunications and consumer applications. this core provides a low-cost, high-performance solution for applications where low-power and portability are a necessity. this core is a component of the lsi logic coreware library, which contains cores for control, high-speed communication, and mixed-signal functions to complement quick time-to-market, customizable solutions. the CWDSP1650 is designed by lsi logic to be fully compatible with the dsp group oakdspcore ? instruction set architecture. the oak family of cores are modi?ed harvard architectures, based on dsp groups pinedspcore ? architecture. the CWDSP1650 architecture contains dedicated buses, program memories, and data memories. the core is composed of three major components: data address arithmetic unit (daau) program control unit (pcu) computation and bit manipulation unit (cbu)
1-2 introduction the cbu includes a multiplier, an arithmetic logical unit (alu), and the bit manipulation unit (bmu). a multiply-accumulate unit performs single- cycle operations. figure 1.1 shows a block diagram of the CWDSP1650 core, with modules external to the core shown as shaded regions. any of the external modules are available as hardmacros from lsi logic and do not need to be generated by the designer. figure 1.1 CWDSP1650 block diagram the CWDSP1650 instruction set allows for straight-forward generation of ef?cient and compact code for implementation of the dsp functions within a system. designers may also integrate multiple oakdspcores onto a single piece of silicon along with other asic functions, processors such as the arm7tdmi core, and application speci?c logic to build a system-on-a-chip. with many instructions available, the CWDSP1650 can also act as a system controller in its own right. interrupts icu pcu ccu pram xram yram daau miu ydb xdb iab idb clocks bmu barrel shifter bfo b0 b1 cbu cu multiplier alu wait edb CWDSP1650 core a0 a1 external registers interrupt acknowledges
features summary 1-3 the CWDSP1650 is supported by a full suite of development tools. support tools for source code and system-level development include: assembler/linker optimizing c compiler simulator on-core emulation module (ocem) evaluation board vhdl or verilog models implement the top-down design methodology. 1.2 features summary this section summarizes the features of the CWDSP1650. 1.2.1 general architecture these features describe general items regarding the hardware architecture of the CWDSP1650: modi?ed harvard architecture single-cycle multiply/accumulate instructions 36-bit arithmetic logical unit (alu) and barrel shifter four 36-bit accumulators saturation mode on over?ow single-cycle exponent evaluation double-precision multiplication support bit ?eld operations four-level zero-overhead nested looping (interruptible) repeat instruction (interruptible) four user interrupts available (three maskable, one nonmaskable) in-circuit debugging support, with on-chip emulator (ocem) automatic context switching with shadow registers software stack support
1-4 introduction six 16-bit data pointers for x-data memory and y-data memory with three additional alternative registers support for direct, indirect, index, and modulo addressing modes off-core x-memory and y-memory facilitating modular design automatic boot procedure support (self and host booting) 1.2.2 memory organization these features describe the memory support of the CWDSP1650. 64 kword addressable data space 64 kword addressable program memory space off-core data memory: up to 64 kwords for x-memory, and up to 32 kwords for y-memory 1.2.3 physical technology these features summarize the physical attributes and technology of the CWDSP1650 dsp core: 0.35-micron g10? technology fully static design 3.3 v 10% operation core power - 2.0 mw/mhz core size - 5.0 mm 2 1.2.4 instruction set summary table 1.1 summarizes the instruction set for the core. all instructions are 16 bits long, and most execute in a single cycle. several instructions including addv, subv, cmpv, and push can optionally have a long immediate operand (due to the long immediate operand, these instructions are executed in two cycles.)
features summary 1-5 table 1.1 CWDSP1650 instruction set summary op description op description arithmetic and logical instructions bmu instructions add add set set bit-?eld sub subtract rst reset bit-?eld or logical or chng change bit-?eld and logical and tst0 test bit-field for zeros xor logical exclusive or tst1 test bit-field for ones cmp compare tstb test speci?c bit addl add to low accumulator shfc shift accumulators according to shift value register conditionally subl subtract from low accumulator addh add to high accumulator shfi shift accumulators by an immediate shift value subh subtract from high accumulator exp evaluate the exponent value cmpu compare unsigned modb modify bx-accumulator conditionally addv add long immediate value 1 modb modi?cations: subv subtract long immediate value 1 shr shift right cmpv compare long immediate value 1 shr4 shift right four norm normalize shl shift left divs division step shl4 shift left four max maximum between two ax-accumulators ror rotate right through carry maxd maximum between data memory location and ax-accumulator rol rotate left through carry clr clear min minimum between two ax-accumulators move instructions lim limit ax-accumulator mov move data moda modify ax-accumulator conditionally movp move from program memory into data memory moda modi?cations: movd move from data memory into program memory shr shift right movs move and shift according to shift value register shr4 shift right four movsi move and shift according to an immediate shift value shl shift left movr move and round shl4 shift left four push push register or long immediate value onto stack ror rotate right through carry pop pop from software stack into register rol rotate left through carry swap swap ax and bx accumulator not logical not banke bank exchange neg two's complement control and miscellaneous instructions clr clear nop no operation copy copy other accumulator modr modify register n rnd round upper 20 bits eint enable interrupt pacr product move and round dint disable interrupt clrr clear and round trap software interrupt inc increment by one load load speci?c field into registers - page, modx, stepx, ps dec decrement by one cntx context switching store or restore
1-6 introduction the CWDSP1650 supports dsp-speci?c instructions such as multiply and accumulate, multiply and subtract, nested block repeat (looping), modulo and index operations on data addresses, bit manipulation operations, and control speci?c operations. see chapter 7, instruction set, for a more detailed description of the core instruction set and an alphabetical listing of all CWDSP1650 instructions. 1.3 coreware program an lsi logic core is a fully de?ned, optimized, and reusable block of logic. it supports industry-standard functions and has prede?ned timing and layout. the core is also an encrypted rtl simulation model for a wide range of vhdl and verilog simulators. the coreware library contains an extensive set of complex cores for the communications, consumer, and computer markets. the library consists of high-speed interconnect functions such as the gigablaze? g10 core, mips embedded microprocessors, mpeg-2 decoders, a pci core, and many more. the library also includes megafunctions or building blocks, which provide useful functions for developing a system on a chip. through the multiply instructions branch/call instructions mpy multiply br conditional branch mpysu multiply signed by unsigned brr relative conditional branch mac multiply and accumulate previous product call conditional call subroutine macsu multiply signed by unsigned and accumulate 2 callr relative conditional call subroutine macus multiply unsigned by signed and accumulate 2 calla call subroutine at location speci?ed by ax-accumulator macuu multiply unsigned by unsigned and accumulate 2 ret return conditionally maa multiply and accumulate aligned previous product retd delayed return reti return from interrupt conditionally maasu multiply signed by unsigned and accumulate aligned 2 retid delayed return from interrupt rets return with short immediate parameter msu multiply and subtract previous product loop instructions mpyi multiply signed short immediate rep repeat next instruction sqr square bkrep block repeat sqra square and accumulate previous product break break from a block-repeat 1. to or from a register or a data memory location. 2. previous product. table 1.1 CWDSP1650 instruction set summary (cont.) op description op description
coreware program 1-7 coreware program, you can create a system on a chip uniquely suited to your applications. each core has an associated set of deliverables, including: rtl simulation models for both verilog and vhdl environments a system veri?cation environment (sve) for rtl-based simulation netlists for full timing simulation complete documentation lsi logic toolkit support lsi logic's toolkit provides seamless connectivity between products from leading electronic design automation (eda) vendors and lsi logic's manufacturing environment. standard interfaces for formats and languages such as vhdl, verilog, waveform generation language (wgl), physical design exchange format (pdef), and standard delay format (sdf) allow a wide range of tools to interoperate within the lsi logic toolkit environment. in addition to design capabilities, full scan automatic test pattern generation (atpg) tools and lsi logic's specialized test solutions can be combined to provide high-fault coverage test programs that assure a fully functional design. because your design requirements are unique, lsi logic is ?exible in working with you to develop your system-on-a-chip coreware design. three different work relationships are available: you provide lsi logic with a detailed speci?cation and lsi logic performs all design work. you design some functions while lsi logic provides you with the cores and megafunctions, and lsi logic completes the integration. you perform the entire design and integration, and lsi logic provides the core and associated deliverables. whatever the work relationship, lsi logic's advanced coreware methodology and asic process technologies consistently produce right-first-time? silicon.
1-8 introduction
2-1 chapter 2 functional description this chapter describes the components and functional blocks of the CWDSP1650 dsp core. this chapter is divided into the following sections: section 2.1, overview section 2.2, buses section 2.3, program control unit (pcu) section 2.4, computation and bit-manipulation unit (cbu) section 2.5, data address arithmetic unit (daau) section 2.6, interrupt control unit (icu) 2.1 overview this section overviews all of the major CWDSP1650 components and the processor pipeline architecture. figure 2.1 contains a block diagram of the CWDSP1650 architecture. (please note that the shaded areas are components external to the core.) this section is further divided into the following subsections: section 2.1.1, CWDSP1650 core components section 2.1.2, CWDSP1650 external modules section 2.1.3, pipeline architecture
2-2 functional description figure 2.1 CWDSP1650 block diagram 2.1.1 CWDSP1650 core components the CWDSP1650 core is composed of the following major elements: CWDSP1650 busses program control unit (pcu) computational and bit manipulation unit (cbu) data addressing arithmetic unit (daau) memory interface unit (miu) interrupt control unit (icu) all CWDSP1650 busses (data and address) are unidirectional and carry data to and from the core. see section 2.2, buses, for more detailed information. the program control unit (pcu) controls the sequencing of the core program: it fetches instructions, generates program memory addresses, handles interrupts with the icu, and sequences branches, calls, and instruction repeats. the pcu generates the control for the rest of the interrupts icu pcu ccu pram xram yram daau miu ydb xdb iab idb clocks bmu barrel shifter bfo b0 b1 cbu cu multiplier alu wait edb CWDSP1650 core a0 a1 external registers interrupt acknowledges
overview 2-3 CWDSP1650 core. see section 2.3, program control unit (pcu), for more detailed information. the computational and bit manipulation unit ( cbu) is composed of two units: the bit manipulation unit (bmu) and the computation unit (cu). the cu contains the multiplier, arithmetic logic unit (alu), and ax accumulators. the bmu contains a barrel shifter, the bit-field operations unit (bfo), and the bx accumulators. the cbu also includes a saturation unit and bus alignment/sign-extension logic available for both the bmu and cu. see section 2.4, computation and bit- manipulation unit (cbu), for more detailed information. the data addressing arithmetic unit (daau) contains the general purpose registers, stack pointer, and index register. it also contains two identical arithmetic units to generate sequences of addresses using the daau registers. two addresses may be generated on each cycle for simultaneous access of both x-memory and y-memory spaces. see section 2.5, data address arithmetic unit (daau), for more detailed information. the memory interface unit (miu) routes data memory addresses to the x- and y-address buses and x-data and y-data from the data memory. the CWDSP1650 user cannot control the miu operations, therefore, the miu is not fully described in this chapter. the interrupt control unit (icu) handles the interrupt protocols for each of the ?ve interrupts and generates a separate acknowledge signal for each one. the icu generates the interrupt vector and status signal for the pcu and also prioritizes incoming interrupts. see section 2.6, interrupt control unit (icu), for more detailed information. 2.1.2 CWDSP1650 external modules besides these internal core components, a CWDSP1650 design may require the following logic blocks external to the core (shaded units in figure 2.1 ): data memory (xram and yram) program memory (pram) external (user de?ned) registers clock control unit (ccu)
2-4 functional description on-chip emulation module (ocem) bus interface unit (biu) 2.1.3 pipeline architecture the CWDSP1650 implements a four-stage pipeline architecture. the pipeline architecture is designed with a central microcode control that allows easier and better control of the core. figure 2.2 shows the CWDSP1650 pipeline operation. figure 2.2 CWDSP1650 instruction pipeline the execution of a single CWDSP1650 instruction consists of the following stages: 1. if (instruction fetch) - the pcu generates a new program address, fetches the instruction, and stores it in the instruction register. 2. id (instruction decode) - the core decodes the instruction into a wide microinstruction that contains almost all the control signals for the CWDSP1650 processor. during the id stage, the core decides the program ?ow and, at the end of the cycle, registers the microinstruction. 3. of (operand fetch and execute) - during the of cycle, the core generates the operand addresses and fetches the source operands from either an internal source or from memory. the core also sets up the alu and other execution units and stores the result in the proper destination. finally, the condition ?ags are updated at the end of the cycle. 4. ex (execute) - this cycle is required only for multiplies and a few other instructions. the multiplier operates on the x and y registers, storing the result in the product register. this result is available during the next of stage. id if of ex
buses 2-5 2.2 buses this section covers the different address and data buses that comprise the CWDSP1650. for this section, the CWDSP1650 buses have been divided into two types: data buses and address buses. 2.2.1 data buses the core transfers data on the following unidirectional 16-bit buses: external main data bus out (edb) instruction data bus in (idb) x-memory data bus in (xdb) y-memory data bus in (ydb) external user register input bus in (ext_in) the external data bus delivers all of the data that passes from the core to the external components (i.e. the xram, yram, pram, and external registers.) the unidirectional ydb bus carries all data transfers from the y-memory to the core. instruction word fetches take place in parallel over the idb. the unidirectional xdb bus carries all data transfers from the x-memory to the core. two 16-bit data words and one instruction word can be moved within one instruction cycle. 2.2.2 address buses the core drives addresses on the following unidirectional 16-bit buses: instruction address bus (iab) x-memory address bus (xab) y-memory address bus (yab) the unidirectional 16-bit x-memory address bus (xab) provides addresses for the x-memory. similarly, the unidirectional 16-bit y-memory address bus (yab) provides the addresses for the y-memory. the unidirectional 16-bit instruction address bus (iab) transfers the program memory addresses to the program memory.
2-6 functional description 2.3 program control unit (pcu) the program control unit (pcu) performs instruction fetch, instruction decoding, interrupt handling, and hardware loop control. it provides control signals for the rest of the CWDSP1650 core and the on-chip emulation unit (ocem). the pcu also provides signals to enable program memory protection in the bus interface unit. figure 2.3 is a block diagram of the pcu and associated logic blocks. figure 2.3 program control unit diagram the pcu contains: instruction register instruction decode logic program counter logic repeat unit at the end of the if cycle, the pcu loads the instruction register with the instruction to be decoded. during the id cycle, instruction decode logic converts the instruction into a number of signals that control the rest of the CWDSP1650 processor. also during the id cycle, the pcu initiates branch or vector operations, depending on the conditions and interrupt states during the cycle. program memory program counter logic instruction register instruction decode logic repeat unit icu conditions interrupts and acknowledges interface to other components iab idb pcu
program control unit (pcu) 2-7 the program counter logic generates the addresses for the program memory and stores the values in the program counter. there are many sources for the program address: current program counter, incremented block repeat start address immediate value (from instruction register) current program counter plus short immediate value interrupt vector special holding register for data access to program memory the repeat unit controls any zero overhead looping operations, initiated by the rep and bkrep instructions. the number of repetitions for a repeat (rep) or block repeat (bkrep) can be de?ned as either an 8-bit ?xed value embedded in the instruction code, or as a 16-bit value transferred from one of the processor registers. a rep instruction repeats the following instruction and a bkrep repeats a block of program code of at least two instructions in length. block repeat loops may be nested up to four levels and a block repeat may contain further rep instructions. both repeat and block repeat loops are interruptible. during the operation of a repeat loop, the repeat unit register (repc) stores the current count of repetitions remaining. the repc value can be read using the instruction mov repc, ab . during the operation of a block repeat loop, the last and ?rst addresses of the loop are stored in dedicated registers in the repeat unit. the loop count is held in the program accessible loop counter (lc). when a block repeat is nested, the start address register, end address register, and lc register for the outer level are stored in the repeat unit, and new values are set up for the new block repeat level. the lp bit in the internal con?guration register (icr) always sets when a block repeat is in progress. resetting the lp bit (with either the mov or icr instruction) stops execution of all current levels of block repeat. the bc[2:0] bits in the icr indicate the current block repeat nesting level. a break instruction can stop each of the four nested levels of a block repeat.
2-8 functional description 2.3.1 interrupt handling in the pcu when the icu responds to an interrupt, it asserts the istat signal and sends the interrupt vector to the pcu. the asserted istat signal causes the id cycle to insert an interrupt service pseudo-instruction into the pipeline, so that the next instruction is prevented from being decoded. instead, the address of the next instruction in the program memory is stored on the stack, and execution continues from the interrupt vector location in the program memory. for more information about the icu, see section 2.6, interrupt control unit (icu). 2.4 computation and bit-manipulation unit (cbu) the computation and bit-manipulation unit (cbu) performs all the arithmetic and logical operations within the core. it contains two main units: the computation unit (cu) and the bit-manipulation unit (bmu). the cbu also contains a saturation unit that is shared by both the cu and the bmu units. 2.4.1 computation unit the computation unit (cu) consists of three major parts: two 36-bit accumulators (a0 and a1) arithmetic logic unit (alu) multiplier unit the following subsections provide details about each of these three functional blocks. figure 2.4 shows a block diagram of the cbu with the cu components shaded.
computation and bit-manipulation unit (cbu) 2-9 figure 2.4 cu block diagram 2.4.1.1 ax-accumulators each ax accumulator is organized as two 16-bit registers (a0h and a0l, a1h and a1l) with a four-bit extension (a0e and a1e). the core accesses the two portions of each accumulator as 16-bit data registers, and uses them as either source or destination registers in all relevant instructions. see section 4.1, cbu registers, for more detailed information on the ax accumulators. 2.4.1.2 arithmetic logic unit the 36-bit arithmetic logic unit (alu) performs all arithmetic and logical operations on data operands. it can perform positive or negative accumulate, add, subtract, compare and several other operations in a single cycle (operations involving immediate data take two cycles). the alu is a 36-bit, single cycle, nonpipelined unit that uses twos complement arithmetic. the alu receives one operand from one of the ax accumulators and another operand from the output shifter of the multiplier, the xdb (through bus alignment logic), or from the other ax accumulator. the bit manipulation unit (bmu) barrel shifter bit-field operations unit b0-accumulator b1-accumulator exponent unit sv register edb saturation unit arithmetic logical unit (alu) multiplier computation unit (cu) a0-accumulator a1-accumulator
2-10 functional description source operands are 8, 16, or 36 bits wide and can be addressed using direct or indirect indexed methods, as a register content or as pointed to by the stack pointer. the source and destination ax accumulators of an alu instruction are always the same. for example, in the instruction add r1, a0 the alu adds register r1 to the a0 accumulator, and stores the result in the a0 accumulator. the alu stores results in one of two ways: 1. in one of the ax accumulators 2. transfers results to one of the registers or a data memory location the alu uses the second method for addition, subtraction, and compare operations between a 16-bit immediate operand and either a data memory location or one of the registers. this method takes two clock cycles and does not affect the accumulators. the add and subtract operations are read-modify-write instructions. for more information see the addv, subv, and cmpv instructions in chapter 7, instruction set. unless otherwise speci?ed, in all operations between an 8-bit or 16-bit operand and a 36-bit ax accumulator, the 16-bit operand is regarded as the least-signi?cant word of a 36-bit operand, with sign extension for arithmetic operations and zero extension for logical operations. the status ?ags in status register 0 and status register 1 are affected as a result of the alu output, the bfo, or the barrel shifter operation. a mov instruction also affects the ?ags when the entire ax accumulator is speci?ed. in most instructions where the alu result transfers to one of the ax accumulators, the ?ags represent the ax accumulator status. 2.4.1.3 multiplier unit the CWDSP1650 uses the twos complement, single-cycle, nonpipelined multiplier for all core multiplication operations. the CWDSP1650 multiplier supports single-precision and double-precision multiplications, and can perform three types of multiplication: signed-by-signed signed-by-unsigned unsigned-by-unsigned
computation and bit-manipulation unit (cbu) 2-11 with the alu and the multiplier, the CWDSP1650 can perform a single- cycle multiply-accumulate (mac) instruction. the multiplier unit implements the instructions listed in table 2.1 . the multiplier unit consists of the following blocks: a 16-bit by 16/32-bit parallel multiplier two 16-bit input registers (x and y) a 32-bit output register (p) a product output shifter input registers (x and y) C the core reads and writes the x and y registers as 16-bit operands. the x and y registers can also be used as general-purpose temporary data registers. see section 4.1.2, x, y, and p registers, for more information. output register (p) C the multiplier unit stores results in this 32-bit register. the core can only move the contents of the p register to the table 2.1 multiplier unit instructions multiply instructions mpy multiply mpyi multiply signed short immediate mpysu multiply signed by unsigned maa multiply and accumulate aligned previous product maasu multiply signed by unsigned and accumulate aligned previous product mac multiply and accumulate previous product macsu multiply signed by unsigned and accumulate previous product macus multiply unsigned by signed and accumulate previous product macuu multiply unsigned by unsigned and accumulate previous product msu multiply and subtract previous product sqr square sqra square and accumulate previous product
2-12 functional description a0 and a1 accumulators. see section 4.1.2, x, y, and p registers, for more information. product output shifter C the p register is sign-extended to 36 bits and then shifted. the data value can be shifted by one bit to the right, one bit to the left, two bits to the left, or left unshifted. for a right shift, the sign is extended to 36 bits; for a left shift, a zero is appended to the lsbs. the ps bits in status register 1 control the shift operations; see section 4.4.2, status register 1 (st1), for more information. double-precision multiplication C the CWDSP1650 supports double- precision multiplication through several multiplication instructions and an alignment option for the p register. in multiply-accumulate aligned instructions (maa and maasu instructions), the p register is aligned (shifted 16 bits to the right) before accumulating the partial multiplication result. example: multiplication of 32-bit by 16-bit fractional numbers, where two multiplications are needed. first, the 16-bit signed multiplier is multiplied with the lower portion of the 32-bit (double-precision) multiplicand using a signed-by- unsigned multiply. then, a signed-by-signed multiplication accumulate operation multiplies the 16-bit signed number with the upper, signed portion of the 32-bit multiplicand and sums this result with the previous result. for the second operation, it is recommended that the aligned result of the ?rst multiplication is accumulated (using maa instruction). for the multiplications of two double-precision (32-bit) numbers, the unsigned-by- signed operation can be used. if this operation requires a 64-bit result, the unsigned-by-unsigned operation should be used. for details on the various multiply instructions, see chapter 7, instruction set. 2.4.2 bit-manipulation unit (bmu) the bit manipulation unit (bmu) provides all functionality for shifting, exponent extraction, normalization, saturation, and sign extension. figure 2.5 shows a block diagram of the cbu with the bmu components shaded.
computation and bit-manipulation unit (cbu) 2-13 figure 2.5 bmu block diagram the bit-manipulation unit (bmu) consists of the following components: a full 36-bit barrel shifter an exponent unit (exp) a bit-field operation unit (bfo) two 36-bit accumulator registers (b0 and b1) a shift value (sv) register 2.4.2.1 barrel shifter the 36-bit barrel shifter performs arithmetic shift, logical shift, and rotate operations. it is a single-cycle, nonpipelined barrel shifter. the barrel shifter receives the source operand from any one of the four accumulators (a0, a1, b0, or b1) or from the edb (through bus alignment logic). either the contents of one of the registers or a data memory location may provide the source operands. source operands can be addressed in either direct memory addressing mode or indirect addressing mode and may be 16 or 36 bits wide. the destination of the edb arithmetic logical unit (alu) multiplier computation unit (cu) a0-accumulator a1-accumulator barrel shifter exponent unit sv register bit-field operations unit b1-accumulator b0-accumulator bit manipulation unit (bmu) saturation unit
2-14 functional description shifted value is always one of the four accumulators. the number of bit shifts applied is determined by a constant embedded in the instruction opcode or by a value in the sv register. when the barrel shifter output is put into one of the accumulators, the status of the ?ag bits represents the accumulator status. see section 4.4.1, status register 0 (st0), for more information on the status ?ag bits. 2.4.2.2 exponent unit the exponent unit (exp) performs exponent evaluation of an accumulator, a data memory location, or a register. the result of this operation is a signed 6-bit value, sign-extended into 16 bits, which is transferred into the shift value register (sv). optionally, it can also be sign-extended into 36 bits and transferred into one of the ax accumulators. the source operand is unaffected by this calculation. the source operand is 36-bits wide when it is an accumulator; 16-bits wide when it is a data memory location or a register. the exponent unit can also be used in ?oating-point calculations, where it is useful to transfer the exponent result into both the sv register and one of the ax accumulators. 2.4.2.3 sv register the CWDSP1650 uses the 16-bit shift value (sv) register for shifting operations and exponent calculation. the sv register value determines the number of shifts during shift operations, and enables the core to calculate the number of shifts at run time. the exponent unit transfers its output to the sv register for use during ?oating point calculations. 2.4.2.4 normalization the CWDSP1650 performs normalization by one of two methods: in the ?rst method, normalization takes two cycles and uses two instructions: exp and shfc. exp evaluates the exponent value of a register, accumulator, or a data memory location. shfc shifts the evaluated number, according to the exponent result stored in the sv register.
computation and bit-manipulation unit (cbu) 2-15 the second method uses the norm instruction. this method is slower and has been retained for compatibility with the pinedspcore instruction set. 2.4.2.5 bit-field operations the bit-field operation unit (bfo) is attached to the alu and sets, resets, changes, or tests up to a 16-bit set within a data memory location or a register. the bfo addresses the data memory location using either a direct or an indirect memory address. the bfo results may affect the ?ag bits in status register 0; see section 4.4.1, status register 0 (st0), for more information on the status ?ag bits. the bfo sets, resets, and changes a 16-bit set with the set, rst, and chng read-modify-write instructions. each instruction requires two cycles and two words, with the 16-bit immediate mask value embedded in the instruction opcode. three bfo testing instructions are available: tst0, tst1, and tstb. tst0 tests up to a 16-bit set for zeroes, tst1 tests for ones, and tstb tests for a speci?c bit (1 out of 16) in a data memory location or in a register. bfo testing (tst0 or tst1) requires either one cycle when the mask is in a0l or a1l, or two cycles when the mask value is embedded in the instruction opcode. tstb always requires a single cycle to execute. for more details refer to the set, rst, chng, tst0, tst1, and tstb instructions in chapter 7, instruction set. 2.4.2.6 bx-accumulators each bx accumulator is organized as two regular 16-bit registers (b0h and b0l, b1h and b1l) with a four-bit extension nibble. the core accesses the two portions of each accumulator as 16-bit data registers, and uses the bx accumulators as 16-bit source or destination data registers in relevant instructions. see section 4.1, cbu registers, for more details on the bx accumulators. 2.4.3 saturation unit the saturation unit ranges the outputs of the four accumulators (a0, a1, b0, b1) to ?t on the internal bus. clearing the sat bit in status register 0 to zero enables the saturation unit, and setting sat to one disables the
2-16 functional description saturation over?ow detection. see section 4.4.1, status register 0 (st0), for more information on the sat bit. the enabled saturation over?ow process works as follows: with saturation enabled, the saturation unit selects one of the four accumulators for transfer and decides whether to transfer the upper or the lower 16 bits of the accumulator. if the accumulator holds an over?owed number (negative or positive number greater than 16 bits), the saturation unit transfers the appropriate maximal (0xffff) or minimal (0x0000) number that can be represented in 16 bits. table 2.2 shows the values the saturation unit transfers with saturation enabled. if the accumulator has not over?owed, the saturation unit transfers the real accumulator value, regardless of the value of the sat ?ag. if the sat bit disables saturation, the accumulator value passed is unaffected, regardless of overflow. saturation arithmetic also selectively limits overflow from the high portion of an accumulator to the sign extension bits. if saturation occurs while performing a move instruction (mov or push) from one of the accumulators, the core does not change the value of the accumulator. the value transferred is limited to a full-scale 16-bit positive or negative value. limiting is performed even if the transfer does not immediately follow the accumulator over?ow. when an accumulator is swapped using the swap instruction, limitation is performed when the value is transferred. the sat bit enables saturation for move instructions. when limiting occurs, the l ?ag in st0 is set to one. the lim instruction activates saturation on a 36-bit ax accumulator. when there is an over?ow from the high portion of an ax accumulator to the extension bits and an lim instruction is executed, the accumulator is limited to a full-scale 32-bit positive (0x7fff ffff) or negative (0x8000 0000) value. limiting is performed even if the lim instruction table 2.2 saturation over?ow value in accumulator transferred value within limits value of bits [31:0] unchanged above positive limit 0xffff below negative limit 0x0000
data address arithmetic unit (daau) 2-17 does not immediately follow the accumulator over?ow. if the core swaps an accumulator, limitation occurs when the value is operated on by the lim instruction. the lim instruction can use the same accumulator for both source and destination or it can use one ax accumulator, which does not change and then transfer the limited result into the other ax accumulator. for more details, refer to the lim instruction in chapter 7, instruction set. when limiting occurs, the l ?ag bit in status register 0 is set. enabling or disabling the sat bit has no effect on the execution of the lim instruction. 2.5 data address arithmetic unit (daau) the data address arithmetic unit (daau) stores all address and effective address calculations necessary to locate data operands in memory. it contains two data address generators and six different data address pointers. the daau provides both linear and modulo arithmetic address generation capabilities. the daau operates in parallel with the computation unit, thus freeing the alu for calculation purposes. figure 2.6 shows a diagram of the daau functional blocks. figure 2.6 data address arithmetic unit (daau) r0b r1b r0 r1 r2 r3 r4b r4 r5 rb index logic cfgj aau2 aau1 cfgi cfgib index addr addr select sp edb xab ya b
2-18 functional description 2.5.1 daau registers the daau contains the following registers: r0-r5 C general purpose and address generation registers. these registers are divided into two groups, r0-r3 and r4-r5. each group is served by its own arithmetic unit. either group can generate addresses for the x data memory on the xab address bus, but only r4-r5 can generate addresses for the y memory. during multiply or multiply- accumulate instructions, a register from each group is used, one from r0-r3 for generating xab and one from r4-r5 for generating yab. r4-r5 can also address program memory during movd and movp instructions. rb C index base register. this register value is added to the offset in index mode addressing. the rb register is part of the global register set and can be used as a general-purpose register. sp C stack pointer. the sp register controls the pre- and post- modi?cation logic used in daau operations. cfgi, cfgj C con?guration registers. these registers specify parameters for modulo addressing and to increment/decrement step control. cfgi and cfgj affect the address arithmetic units results during modi?cation of r0-r5. the cfgi register is used for registers r0- r3 and cfgj for registers r4-r5. r0b, r1b, r4b, cfgib C context switch registers for the r0, r1, r4, and cfgi registers. after a daau address pointer (rn) accesses the memory, it can be postmodi?ed through the step ?eld in the con?guration registers. a length value can be associated with each pointer to implement step modi?cation of the pointer. the con?guration registers also provide supports for circular buffers through automatic up/down modulo addressing. the rn registers may also be used for loop control. the modr instruction sets the r ?ag in status register 0 if the rn register being modi?ed is zero following its execution. conditional branch instructions dependent on the value of the r ?ag can then implement loops.
data address arithmetic unit (daau) 2-19 2.5.2 addressing modes the daau can generate data memory addresses using a number of different methods: long direct addressing short direct (paged) addressing stack pointer operations indexed addressing indirect addressing these addressing modes can be used to create data memory structures for circular buffers, delay lines, fifos, other pointers to the software stack. the following subsections describe each addressing mode in more detail. 2.5.2.1 long direct addressing mode long direct addressing mode uses 16 bits embedded in the instruction opcode as the 16-bit data memory address. any location in the 64 kword memory space can be directly addressed in two cycles. 2.5.2.2 short direct addressing mode short direct addressing uses eight bits embedded in the instruction opcode as the lsb plus eight bits from the page ?eld of status register 1 as the msb to compose the 16-bit data memory address. the page ?eld can then be set to values between 0 and 255, where page 0 corresponds to addresses 0 to 255 in xram. this addressing mode allows for single cycle data memory access. 2.5.2.3 stack pointer operations the core can use rb as either an array pointer or in conjunction with the stack pointer (sp). when the stack is used for transferring subroutine parameters, initializing rb with the value of the sp enables quick access to these parameters. this method of operation is particularly useful for high level language compilers, when rb can be used as a frame pointer to hold the value of the sp as subroutines are entered.
2-20 functional description the stack pointer is predecremented for a push operation and postincremented for a pop operation. in other words, the stack grows from a high memory address towards a low memory address. 2.5.2.4 indexed addressing mode indexed addresses are derived by adding an offset to the rb register. the offset is either a signed short immediate 7-bit value derived from a ?eld of the instruction opcode or a 16-bit immediate value (a second instruction word). the base register content is unaffected by the instruction. notice that the index addressing mode, unlike the linear and modulo addressing modes, uses address premodi?cation and not postmodi?cation. 2.5.2.5 indirect addressing modes the indirect addressing method uses addresses taken from the r0-r5 registers to provide data or program (in movp and movd instructions) memory addresses. these registers can be postmodi?ed by the aaus with a linear or modulo operation. table 2.3 lists the registers and bit ?elds used during the indirect addressing modes. each rn address register has a corresponding modulo enable bit in st2. setting one of the mn bits to one enables modulo addressing for the rn bit, and clearing the mn bit to zero disables modulo calculation mode. the modi and modj bit ?elds of the cfgi and cfgj registers contain the modulo values to be used in the modulo calculation; the stepi and stepj bit ?elds contain the linear modi?ers. please remember that cfgi (modi/stepi) modi?es only the r0-r3 registers, while cfgj (modj/stepj) is used exclusively with the r4-r5 registers. linear (step) modi?cation C in linear modi?cation, the pointer (rn) is modi?ed by postincrementing by one, postdecrementing by one, or table 2.3 indirect addressing mode bits address registers enable bits (st2) con?guration registers modulo bit field linear bit field r0-r3 m0-m3 cfgi modi stepi r4-r5 m4-m5 cfgj modj stepj
data address arithmetic unit (daau) 2-21 adding the value speci?ed in the stepi/stepj ?eld of the corresponding cfgi/cfgj register. the step bit ?eld value is a twos complement seven-bit number that ranges from -64 to +63. modulo modi?cation C modulo and linear modi?cation methods operate in a similar fashion, except that the range of address values is limited by the modi/modj bit ?elds of the cfgi/cfgj registers. the modi/modj ?elds are nine bits in length and can specify circular buffers of up to 512 (2 9 ) words.the six mn bits in st2 enable modulo calculation for each register. the modi and modj ?elds in the cfgi and cfgj registers determine the modulo settings. one address register from each group may be updated in a single instruction cycle. modulo constraints C for modulo calculation, the following constraints must be satis?ed (m = modulo factor; q = stepx, +1 or -1): 1. only the p least-signi?cant bits (lsbs) of rn can be modi?ed during modulo operation, where p is the minimal integer that satisfies 2 p 3 m. rn should be initiated with a number whose p lsbs are less than m. 2. the constraints when modulo m is a power of 2 (full modulo operation): C the lower boundary (base address) must have zeros in at least the k lsbs, where k is the minimal integer that satis?es 2 k >m-1. C modn (n denotes either i or j) must be loaded with m C |q|, where |q| denotes the absolute value of q. Cm 3 q. 3. the constraints when modulo m is not a power of 2: C the lower boundary (base address) must have zeros in at least the k least-signi?cant bits, where k is the minimal integer that satis?es 2 k > m C |q|. C modx (x denotes i or j) must be loaded with m C |q|. C m must be an integer multiple of q (always true for q = 1). C rn should be initialized with a value that contains an integer multiple of |q| or zeros in its k least-signi?cant bits.
2-22 functional description modulo modi?er operation C the modulo modi?er operation, which is a postmodi?cation of the rn register, is de?ned as follows: rn ? 0 in k lsb; if rn is equal to modx in k lsbs and q 3 0, rn ? modx in k lsb; if rn is equal to 0 in k lsbs and q < 0, rn (k lsbs) ? rn+q (k lsbs); otherwise when m = |q| (for example, modx = 0), modulo operation is: rn ? rn. modulo and step example 1 C for m = 7 with stepx = 1 (or +1 selected in instruction): modx = 7 C 1 = 6, rn = 0x0010. the sequence of rn values is: 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0010, 0x0011, and so on. modulo and step example 2 C for m = 8 with stepx = 2: modx = 8 C 2 = 6, rn = 0x0010. the sequence of rn values is: 0x0010, 0x0012, 0x0014, 0x0016, 0x0010, 0x0012, and so on. modulo and step example 3 C for m = 9 with stepx = -3: modx = 9 C |-3| = 6, rn = 0x0016. the sequence of rn values is: 0x0016, 0x0013, 0x0010, 0x0016, 0x0013, and so on. modulo and step example 4 C for m = 8 with stepx = 3, (2 3 = 8) - full modulo support: modx = 8 C 3 = 5, rn = 0x0010. the sequence of rn values is: 0x0010, 0x0013, 0x0016, 0x0011, 0x0014, 0x0017, 0x0012, 0x0015, 0x0010, 0x0013, and so on.
interrupt control unit (icu) 2-23 2.6 interrupt control unit (icu) figure 2.7 shows the interrupt control unit (icu). figure 2.7 interrupt control unit the icu implements the protocol for the ?ve external interrupts: bi/trap, nmi, i0, i1 and i2. each interrupt has its own acknowledge, so there are ten signals in all. interrupts are sampled on the rising edge of icu_clk, which is a copy of the core clock but is not affected by wait states. once sampled as active, an interrupt is held until serviced, no matter what the behavior of the interrupt request signal. if two interrupts occur simultaneously (or nearly simultaneously) such that both sampled and held in the icu together, then logic in the icu prioritizes them, in the order from bi/trap (highest), nmi, i0, i1, to i2 (lowest), and services the highest priority interrupt ?rst. the icu generates an interrupt status signal (istat) to the pcu and an interrupt vector. the interrupt vector is a program location to which program control will jump when the interrupt is serviced. see section 6.3, interrupts, for more information about interrupts, the interrupt signals, and interrupt priority. when the pcu services the interrupt request from the icu, it signals the icu to acknowledge that interrupt and remove the interrupt status condition. only one interrupt is acknowledged on its own dedicated acknowledge line to avoid clearing interrupts that have not been serviced. the off-core logic must remove the interrupt request before another interrupt can be serviced for a speci?c request line. nonmaskable interrupt interrupts icu pcu interrupt acknowledges 5 3 bi/trap interrupt edb
2-24 functional description
3-1 chapter 3 data formats, memory and addressing the CWDSP1650 allocates two independent memory spaces: the data space and the program space. the data and program memory spaces are both 64 kwords in size. the data memory space is further divided into the x-memory and y-memory spaces to support parallel data moves. this chapter describes the mapping of the program and data spaces and the different addressing modes to and from these spaces. this chapter contains the following sections: section 3.1, data formats section 3.2, program memory section 3.3, data memory 3.1 data formats the CWDSP1650 supports six integer formats: 16-bit signed integers 16-bit unsigned integers 32-bit signed integers 32-bit unsigned integers 36-bit signed integers 36-bit unsigned integers figure 3.1 shows the signed and unsigned integer formats. in the ?gure, an s in bit 15 or 31 refers to the sign bit.
3-2 data formats, memory and addressing figure 3.1 signed and unsigned integer formats table 3.1 lists the valid ranges for the signed and unsigned integer formats. unsigned 16-bit value 15 0 integer signed 16-bit value 15 14 0 s integer unsigned 32-bit value 31 0 integer signed 32-bit value 31 30 0 s integer unsigned 36-bit value 35 0 integer signed 36-bit value 35 34 0 s integer
data formats 3-3 in general, the core performs arithmetic operations in 2s complement and treats the numbers as signed. some exceptions do occur, however, depending on the speci?c instruction. only the accumulators can support 36-bit integers. usually, the accumulators are seen as 36-bit signed registers or 32-bit registers if the extension bits are not used (they are the same as bit 31, the sign bit). the add a0, a0 instruction can involve either two 36-bit signed numbers or two 32-bit signed numbers. see section 4.1, cbu registers, for more information on the accumulators. the macuu instruction multiplies two unsigned numbers and stores the result, which is a 32-bit unsigned number, in the p register. a subsequent instruction that transfers the p register into an accumulator results in a 36-bit unsigned number in the accumulator. in most cases, a 16-bit register is used as a signed 16-bit number (for example, add r1, a1 ). whether the register is signed or unsigned depends on the instruction. for example, in the instruction add r1, a0 r1 is treated as a signed 16-bit number. but for the instruction addl r1, a0 r1 is treated as an unsigned 16-bit number. the loop counter (lc) register can be used as a loop counter in the bkrep instruction. in this case, the register value is unsigned. however, the lc register can also be used as a general-purpose register in the add lc, a0 instruction. in this case, the lc register value is signed. see chapter 4, registers, for more information on the lc register and the p register. table 3.1 signed and unsigned integer ranges data type width (bits) lower limit upper limit signed 16 -2 15 2 15 C1 unsigned 16 0 2 16 C1 signed 32 -2 31 2 31 C1 unsigned 32 0 2 32 C1 signed 36 -2 35 2 35 C1 unsigned 36 0 2 36 C1
3-4 data formats, memory and addressing 3.2 program memory the program memory address space is contained in an off-core pram module and encompasses the program code, program constants, interrupt routines, and reset routines. figure 3.2 shows the program memory map. figure 3.2 program memory map addresses 0x0000 C 0x0016 contain the vector addresses for: reset trap/bi (software/hardware interrupt) nmi (nonmaskable interrupt) maskable interrupts (interrupts 0, 1, and 2) the reset, trap/bi, and nmi vectors are separated by two locations so that branch instructions can be accommodated in those locations, if desired. the maskable interrupt vectors are separated by eight words, so fast interrupt service routines can be accommodated without branch statement delays. note that the trap/bi interrupt vector addresses are reserved for use by the emulator during debug. main program interrupt 2 interrupt 1 interrupt 0 nmi trap/bi reset 0x0000 0x0002 0x0004 0x0006 0x000e 0x0016 0x001e 0xffff
data memory 3-5 the CWDSP1650 supports an off-core wait-state generator to help interface slow program memory devices. to provide this ability, the wait- state generator provides a wait input to the core that stops the core clock when asserted. this functionality is usually implemented within the off-core clock control unit. the CWDSP1650 also supports internal program memory protection. this mechanism allows the implementation of a secured version of an internal program-based chip, which protects the internal program memory from being read without proper authorization. see section 6.6, program protection mechanism, for more details about the protection operation. 3.2.1 program memory addressing modes program memory addresses are generated by the program control unit (pcu), which performs all instruction fetching, exception handling and loop control. for the CWDSP1650, the program memory can be addressed either in indirect addressing mode, or in special relative addressing mode. 3.2.1.1 indirect addressing mode in this mode, the rn registers of the daau and the accumulators are used for addressing the program memory (used in the movd and movp instructions.) 3.2.1.2 special relative addressing mode in this mode, branch-relative (brr) and call-relative (callr) instructions support jumping relative to the pc (from pc C 63 to pc + 64) that facilitates smaller and more easily relocatable code. 3.3 data memory the CWDSP1650 data memory space is divided into separate x-memory and y-memory spaces to allow single cycle parallel data accesses. the size and con?gurations of these memories are determined according to the mem_cfg[2:0] core input. table 3.2 lists the x-memory and y-memory con?gurations available and the corresponding mem_cfg[2:0] value.
3-6 data formats, memory and addressing the x-memory and y-memory can contain ram, rom, and i/o. the core also uses memory-mapped i/o; several addresses of the data space may be reserved for peripherals, depending on the speci?c chip con?guration. the core implements slow peripheral interfacing through an off-core biu, which controls the number of wait states. to control the wait states, the biu uses the wait input of the core to stop core_clk during wait stated accesses. 3.3.1 data memory addressing modes the CWDSP1650 supports ?ve data memory addressing modes: short direct long direct indirect short index long index the software stack, which is located in the data memory, is addressed using the stack pointer (sp) register. see section 4.2.4, stack pointer register (sp), for more information. table 3.2 data memory address mapping mem_cfg[2:0] y-memory x-memory size (words) address range size (words) address range 000 32 k 0x8000 to 0xffff 32 k 0 to 0x7fff 001 16 k 0xc000 to 0xffff 48 k 0 to 0xbfff 010 8 k 0xe000 to 0xffff 56 k 0 to 0xdfff 011 4 k 0xf000 to 0xffff 60 k 0 to 0xefff 100 2 k 0xf800 to 0xffff 62 k 0 to 0xf7ff 101 1 k 0xfc00 to 0xffff 63 k 0 to 0xfbff 110 512 0xfe00 to 0xffff 63.5 k 0 to 0xfdff 111 256 0xff00 to 0xffff 63.75 k 0 to 0xfeff
data memory 3-7 3.3.1.1 short direct addressing in the short direct con?guration, the 16-bit address is generated by appending the 8-bit page ?eld from status register 1 to the 8 lsbs of the opcode (i.e. the page ?eld forms the msb of the address). each page consists of 256 words, as shown in table 3.3 . in short direct addressing, all memory locations in the 64-kword space can be directly accessed in a single cycle. 3.3.1.2 long direct addressing in the long direct con?guration, the 16-bit address is taken directly from the opcode as the second word of the instruction. using long direct addressing, all memory locations in the 64 kword space can be directly accessed in two cycles. 3.3.1.3 indirect addressing indirect addressing has two stages: address generation and pointer postmodi?cation. the rn registers (pointers) of the daau are used as 16-bit addresses for indirect addressing the x-memory and y-memory. in one-operand addressing, one pointer supplies the address for the transaction. in two-operand addressing, two pointers simultaneously select the address to the x-memory and y-memory spaces. see section 2.5.2.5, indirect addressing modes, for details of pointer postmodi?cation. table 3.3 short direct addressing page values page x-memory address range 0 0 to 255 1 256 to 511 ... ... 255 0xff00 to 0xffff
3-8 data formats, memory and addressing 3.3.1.4 short index addressing the base register rb plus an index value (offset7) are used for index- based indirect addressing of the x-memory or the y-memory. the index value is a short immediate value embedded in the instruction opcode (offset7), and can range from -64 to +63. the actual address is rb + offset7, the rb contents being unaffected by the operation. 3.3.1.5 long index addressing the contents of base register rb plus a 16-bit immediate index value are used for index-based indirect addressing of the x-memory and y-memory. the immediate index value is embedded in the instruction opcode, and can range from -32768 to +32767. the contents of rb are unaffected.
4-1 chapter 4 registers this chapter describes the CWDSP1650 registers in detail and de?nes the bit ?elds within them. chapter 4 is further divided into the following sections: section 4.1, cbu registers section 4.2, daau registers section 4.3, pcu registers section 4.4, status registers section 4.5, user-de?ned registers figure 4.1 shows the accessible registers/counters in their respective functional blocks within the core. internal CWDSP1650 functional blocks are shown inside the shaded area. figure 4.1 CWDSP1650 registers user-de?ned ext0 ext1 ext2 ext3 registers cbu pcu pc lc repc icr dvm daau r0 r4 r1 r5 r2 r3 cfgi cfgj sp rb mixp status st0 st1 st2 registers bmu b0h b1h b0l b1l sv cu a0e a0h a1e a1h a0l a1l x y p
4-2 registers the following sections contain detailed descriptions for each of these components and their programmable registers. unless otherwise stated, all on-core registers, accumulators and counters clear to zero after reset. 4.1 cbu registers the computation and bit manipulation unit contain four accumulators (a0, a1, b0, b1), two multiplier input registers (x, y), a multiplier product register (p), and a shift value register. table 4.1 lists the cbu registers; the remainder of this section describes each register set in detail. 4.1.1 ax and bx accumulators there are four accumulators: two ax accumulators in the computation unit (cu), and two bx accumulators in the bit manipulation unit (bmu). each accumulator is organized as two regular 16-bit registers with 4-bit extensions as shown in table 4.2 . table 4.1 cbu registers register abbreviations page ax accumulators (axe, axh, or axl) 4-3 bx accumulators (bxe, bxh, or bxl) 4-5 x register C 4-6 y register C 4-6 p register C 4-6 interrupt context switching registers C 4-7 shift value register sv 4-9
cbu registers 4-3 the core accesses the upper and lower portions of each accumulator as separate 16-bit data registers and uses them as 16-bit source or destination registers in all relevant instructions. saturation arithmetic selectively limits over?ow from the high portion of an accumulator to the extension bits, when performing a move instruction from one of the accumulators through the edb, or when using the lim instruction which forces saturation on the 36-bit accumulator. for more information about saturation, see section 2.4.3, saturation unit. all four accumulators clear to zero after a core reset. 4.1.1.1 ax accumulators (a0 and a1) the ax accumulators store the source/destination operands of the alu, barrel shifter, or exponent unit. axh and axl may also be used as general purpose 16-bit data registers. extension nibbles C 4-bit extension nibbles a0e and a1e protect against 32-bit over?ow. these two nibbles are accessed as bits 15 to 12 of the status registers st0 (for a0e) and st1 (for a1e). when the result of an alu output crosses bit 31, the extension flag (e) in st0 is set, which indicates a crossing of the axh msb. an extension nibble allows for up to 15 over?ows or under?ows. when one of these limits is exceeded, the sign is lost beyond the msb of the alu output and/or the extension nibble msb. when this happens, the over?ow flag (v) is set, which also causes the limit flag (l) to be set. refer to section 4.4, status registers, for more details on the extension, over?ow, and limit ?ags. table 4.2 ax and bx accumulator organization accumulator upper 16-bit register lower 16-bit register 4-bit extension a0 a0h a0l a0e a1 a1h a1l a1e b0 b0h b0l b0e b1 b1h b1l b1e
4-4 registers sign extension C the core normally sign extends smaller operands written to the 16-bit axl or axh registers within the 36-bit ax accumulators. this can happen when data from either the edb, the alu, or the exponent unit (during some cbu operations) is written to one of these accumulators. speci?c instructions can also be used to suppress sign extension, for example, mov 100, a0, eu . see chapter 7, instruction set, for details. loading of ax accumulators C when an instruction loads an ax accumulator with a 16-bit data value, the complete 36-bit word of the accumulator is affected as shown in table 4.3 , depending on how the accumulator is speci?ed in the instruction ?eld: for example, the instruction mov r0, a1l loads a 16-bit value into a1l, and sign extends a1h; the instruction mov r1, a1h loads a 16-bit value into a1h, and clears a1l. the instructions addl and addh are exceptions. the addl instruction treats the 16-bit source operand as an unsigned number, extends this number to 36 bits by adding zeroes, and adds the result to the destination 36-bit ax accumulator. the addh instruction loads a 16-bit value into axh, but leaves axl unaffected. an instruction that loads a 36-bit value into an ax accumulator does not follow the above rules, such as a shift instruction or the swap instruction. see section 4.1.1.3, swapping the accumulators, for a detailed account of accumulator swapping, and chapter 7, instruction set, for more information on the mov, addl, addh, and swap instructions. table 4.3 ax accumulator loading values accumulator eu 1 1. extension unaffected. see table 7.4 for a more complete description. accumulator fields after instruction execution axe axh axl ax C sign-extended sign-extended data axl C cleared cleared data axh C sign-extended data cleared axh eu unaffected data cleared
cbu registers 4-5 4.1.1.2 bx accumulators (b0 and b1) each bx accumulator is either a source operand of the bmu exponent unit or a source/destination operand of the bmu barrel shifter. extension nibbles C extension nibbles b0e and b1e protect against 32-bit over?ows. when the result of the barrel shifter crosses bit 31, it sets the extension flag (e) in status register 0, which indicates a crossing of the bxh msb. when the sign is lost beyond the msb of the barrel shifter and/or the msb of the extension nibble, the over?ow (v) and limit (l) ?ags in status register 0 are set. see section 4.4, status registers, for more details about the extension, over?ow, and limit ?ags. the extension bits b0e and b1e are not accessible directly. they can be accessed with the aid of a single-cycle shift instruction, or by swapping to the ax accumulator. sign extension C the core normally sign extends smaller operands written to the 16-bit bxl or bxh registers within the 36-bit bx accumulators. this can happen when either data from the edb or the barrel shifter (in shift operations) is written to the bx accumulators. loading of bx accumulators C when an instruction loads a bx accumulator with a 16-bit data value, the 36-bit accumulator is affected as shown in table 4.4 , depending on how the accumulator is speci?ed in the instruction ?eld. for example, the instruction mov r0, b1l loads a 16-bit value into b1l, and sign extends b1h; the instruction mov r1, b1h loads a 16-bit value into b1h, and clears b1l. however, an instruction that loads a 36-bit table 4.4 bx accumulator loading values accumulator accumulator fields after instruction execution bxe bxh bxl bx sign-extended sign-extended data bxl cleared cleared data bxh sign-extended data cleared
4-6 registers value into a bx accumulator does not follow the above rules, such as using shift instructions or swap instruction. see section 4.1.1.3, swapping the accumulators, for a detailed account of accumulator swapping, and chapter 7, instruction set, for more information on the mov, add, and swap instructions. 4.1.1.3 swapping the accumulators the swap instruction swaps the contents of the ax accumulators and the bx accumulators in a single cycle. either two 36-bit registers or all four 36-bit registers can be swapped in one cycle. swapping can also be enabled between a speci?c ax accumulator and a speci?c bx accumulator such that, in the same cycle, a bx accumulator is swapped with an ax accumulator. similarly, swapping is enabled between a specific bx accumulator into an ax accumulator, and in the same cycle from that ax accumulator into another bx accumulator. for a summary of the 14 swap options, refer to the swap instruction in chapter 7, instruction set. 4.1.2 x, y, and p registers the x, y, and p registers are part of the multiplier unit in the cu and can be used as general-purpose data registers. for more information about these three registers, see section 2.4.1.3, multiplier unit. the 16-bit x and y registers are input registers, which the core reads or writes as 16-bit operands. the core receives information from the x register through the xdb and from the y registers through the ydb; the core writes through the edb for both registers. both the x and y registers clear to zero after reset. the 32-bit p register is used to store multiplication results, and can be shifted prior to input into the alu or to support double precision multiplication. the contents of the p register can only be moved to the ax accumulators. the most-signi?cant 16 bits of the p register (ph) can be written through the edb bus, which enables a single-cycle restore of these bits during an interrupt service routine. the core updates the p register only after a multiply instruction and not after a change in the input registers. figure 4.2 shows the p register bit ?eld.
cbu registers 4-7 figure 4.2 p register the p register supports double-precision during a multiply instruction. to shift the partial multiplication result, the contents of the p register is shifted 16 bits to the right before the contents are accumulated. for more details, see the multiply instructions in chapter 7, instruction set. 4.1.3 interrupt context switching registers when an interrupt occurs the contents of the registers used by the interrupt service routine must be saved. this allows the original program to safely resume operation after the interrupt service routine is complete. to reduce the overhead of saving these registers, the core can optionally activate a context switching mechanism for the interrupts nmi, int0, int1, and int2. setting the corresponding bit in the icr activates the context switching mechanism for the speci?ed interrupt. see section 4.3.2, internal con?guration register (icr), for more information on the context switching enable bits (ic[2:0], nmic). if an interrupt occurs while context switching is enabled, certain registers are saved automatically without an increase in interrupt latency. when returning from the interrupt service routine the original register values are restored automatically (see the reti and cntx instructions in chapter 7, instruction set, for more information.) context switching involves three parallel mechanisms: 1. push to/pop from dedicated shadow bits 2. swap of a dedicated page register 3. swap between the a1 accumulator and b1 accumulator the core saves the st0[0], st0[11:2], st1[11:10], and st2[7:0] register bits automatically as shadow bits (in a one stack level register.) the data bits can be pushed to or popped from the shadow registers. figure 4.3 shows the shadow register mapping for status register 0. 31 16 15 0 ph pl
4-8 registers figure 4.3 st0 and shadow registers figure 4.4 shows the shadow and alternative registers available for the shadow mapping of status register 1. figure 4.4 st1 and shadow registers the core swaps the page bits in st1[7:0] to an alternative register instead of the shadow register. when a context switch occurs, the current page is saved into the alternative register, and the previous (stored) value of the page is restored. the stored value should point to the interrupt page to avoid additional initialization. when returning from the interrupt, the interrupt page is saved again into the alternative register for the next interrupt, and the page used before entering the interrupt service routine is swapped with the page bits in st1. the alternate page bits are not accessible directly. they can be set up through the normal page bits using the cntx instruction. figure 4.5 shows the shadow register mapping for status register 2. 15 1211109876543210 a0e z m n v c e l r im1 im0 ie sat shadow z m n v c e l r im1 im0 sat 15 12 11 10 9 8 7 0 a1e ps res page shadow ps alternative page
daau registers 4-9 figure 4.5 st2 and shadow registers during a context switch the core can automatically swap the a1 accumulator and b1 accumulators, therefore, it is normally convenient to store data needed for interrupt routines in the b1 accumulator. 4.1.4 shift value register the CWDSP1650 uses the 16-bit shift value (sv) register for shifting operations and exponent calculation. the value in sv determines the number of shifts during shift operations, and enables the core to calculate the number of shifts at run time. the exponent unit transfers its output to the sv register for use during ?oating point calculations. this register can also be used as a general-purpose data register. the sv register clears to zero after reset. 4.2 daau registers this section describes the data address arithmetic unit (daau) registers. these registers are normally used in generation of addresses but some can also be used as general purpose 16-bit registers. further information about how to use these registers is available in section 2.5, data address arithmetic unit (daau). table 4.5 lists all daau registers, with descriptions of each in the following subsections. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ip1 ip0 ip2 res iu1 iu0 ou1 ou0 s im2 m5 m4 m3 m2 m1 m0 shadow s im2 m5 m4 m3 m2 m1 m0
4-10 registers 4.2.1 address registers (r0-r5) the six 16-bit address registers (rn) are divided into two groups: r0 to r3, and r4 to r5. these registers can be used to accesses x and y memory spaces or program memory space as shown in table 4.6 . the CWDSP1650 can simultaneously access data in x and y memory spaces during multiply operations. for example, mac (r4), (r0), a0 performs a multiply on the y space data (pointed to by r4) and the data in x space (pointed to by r0) and adds the result to accumulator a0. the rn registers can also be used as loop counters with the modr instruction, which is used to increment or decrement the rn registers. the r ?ag in status register 0 is set if the modr (or any rn modi?cation operation) results in that rn register being set to zero. refer to the r ?ag in section 4.4.1, status register 0 (st0), for more information. table 4.5 daau registers register abbreviations page address registers 0-5 r0-r5 4-10 con?guration registers cfgi, cfgj 4-11 base register rb 4-11 stack pointer register sp 4-12 alternative bank registers r0b, r1b, r4b, cfgib 4-12 min/max pointer latching register mixp 4-13 table 4.6 rn register grouping address bus associated rn registers xab r0 through r5 yab r4 through r5 iab r4 through r5
daau registers 4-11 4.2.2 con?guration registers the con?guration registers, cfgi and cfgj, de?ne the modulo and/or step values for the addressing modes used in conjunction with the rn registers. they are split into two different ?elds: the step ?eld and the modulo ?eld. the step ?eld is used in linear and modulo modes, and the modulo ?eld is used only in modulo mode. table 4.7 shows when these ?elds are valid in these modes. see section 2.5.2, addressing modes, for information on how the two ?elds affect the rn register pointers. figure 4.6 shows the cfgi register bit ?elds, and figure 4.7 shows the cfgj register bit ?elds. the cfgi and cfgj registers clear to zero after reset. figure 4.6 cfgi con?guration register figure 4.7 cfgj con?guration register cfgi is associated with r0Cr3, and cfgj is associated with r4Cr5. this enables simultaneous addressing over both the xab and either the yab or the iab. 4.2.3 base register (rb) the rb register is used in indexed addressing mode to define the base address of the data being addressed. see section 2.5.2.4, indexed addressing mode, for further information. rb can also be used as a 16-bit general-purpose register. the rb register clears to zero after reset. table 4.7 validity of step and modulo in different addressing modes mode step field valid modulo field valid linear yes no modulo yes yes 15 7 6 0 modi stepi 15 7 6 0 modj stepj
4-12 registers 4.2.4 stack pointer register (sp) the CWDSP1650 provides a software stack up to 64 kwords in size. the 16-bit stack pointer (sp) is a global register that points to the address of the top value in the stack, which is also the last value pushed onto the stack. the stack ?lls from high-memory addresses to low-memory addresses. values can be pushed to and popped from the stack using the push and pop instructions. a pop instruction postincrements the sp; a push instruction predecrements the sp. the program counter (pc) is automatically pushed onto the stack whenever a subroutine call or an interrupt occurs and popped off the stack upon execution of return opcodes. the sp register clears to zero after reset. to bypass the pop mechanism, execute the instruction mov (sp), reg , which causes memory to be read from an address pointed to by the sp. the mov instruction reads the top of the stack without affecting the sp. the software stack can reside anywhere in the data space (x-memory or y-memory). the rn and rb registers can also access the stack. the stack generally is used for transferring parameters to subroutines and for automatic variables (such as local subroutine variables). thus, after the initialization of the base register (rb) with the sp value, the mov, add, sub, cmp, and, or, and xor instructions can typically directly access subroutine parameters using the indexed addressing mode. 4.2.5 alternative bank registers the daau contains an alternative bank of four registers: r0b, r1b, r4b, and cfgib. these are the alternatives to the normal registers r0, r1, r4, and cfgi. only one of each pair of normal and alternative registers is accessible at a time, with the bank selection made through the banke instruction. the alternative registers can be used as required by the programmer, typically for interrupt service routines. the banke instruction exchanges (swaps) the contents of the current register with the alternative register. the instruction includes a list of registers to be exchanged in a single cycle. up to 4 registers can be included in the list. table 4.8 shows the address or con?guration registers with their corresponding alternative bank registers. the register r0b, r1b, r4b, and cfgib clear to zero after reset.
pcu registers 4-13 4.2.6 minimum/maximum pointer latching register (mixp) mixp is a 16-bit register that is used to latch the value of the r0 register during min/max operations. note that the mixp register cannot be read in the instruction immediately following the max/min instruction. the mixp register can also be used as a general-purpose 16-bit register and is cleared to zero after reset. 4.3 pcu registers the core uses the program control unit registers to control program ?ow, interrupts, loops, and to support on-chip emulation. see section 2.3, program control unit (pcu), for additional information about the pcu architechture. table 4.9 lists all the pcu registers described in this section. table 4.8 alternative bank registers address /con?guration register alternative bank register r0 r0b r1 r1b r4 r4b cfgi cfgib table 4.9 pcu registers register abbreviations page data value match register dvm 4-14 internal con?guration register icr 4-14 program counter pc 4-15 loop counter lc 4-15
4-14 registers 4.3.1 data value match register the 16-bit data value match (dvm) register supports the optional on-chip emulation module (ocem), which resides off-core. the ocem uses the dvm to generate a breakpoint on a data value match. a data value match occurs when the dvm register content is the same as the data on the edb. the dvm register is on-core in order to enable comparisons for any transaction, since data is not always transferred off- core. the dvm register clears to zero after reset. the dvm register is also used during the service of a software trap. the contents of the program counter (pc) is transferred to the dvm register and to the software stack. the dvm register contents can only be transferred through the ax and bx accumulators. 4.3.2 internal con?guration register (icr) figure 4.8 shows the format of internal con?guration register (icr). the icr includes the context switching bits and the block-repeat indication. a core reset clears all bits in the icr to zero. figure 4.8 internal con?guration register (icr) res reserved [15:8] these bits are reserved for lsi logic. these bits always read as zero and are not affected by a write. bc[2:0] block repeat nesting counter [7:5], r these bits hold the current block-repeat loop nesting level. the bcx bits are read only. 15 876543210 res bc2 bc1 bc0 lp ic2 ic1 ic0 nmic bc2 bc1 bc0 block-repeat counter state description 0 0 0 not within a block-repeat loop 0 0 1 first block-repeat level (outer loop) 0 1 0 second block-repeat level 0 1 1 third block-repeat level 1 0 0 fourth block-repeat level (inner loop)
pcu registers 4-15 the bcx bits clear when either the processor resets, or the lp bit clears to zero. lp inloop 4, r/w lp is set when a block loop repeat occurs; otherwise, lp is cleared to zero. clearing lp also clears the block repeat nesting counter bits (bcx). writing a zero to the lp bit has no effect. writing a one to lp clears the bit to zero and also causes a break from all current levels of block repeat nesting. for more information on block repeats, see section 2.3, program control unit (pcu). ic2 int2 context switching enable 3, r/w ic2 is the context switching enable for int2. setting ic2 enables context switching when an int2 interrupt occurs. clearing ic2 disables context switching for the int2 interrupt. ic1 int1 context switching enable 2, r/w ic1 is the context switching enable for int1. setting ic1 enables context switching when an int1 interrupt occurs. clearing ic1 disables context switching for the int1 interrupt. ic0 int0 context switching enable 1, r/w ic0 is the context switching enable for int0. setting ic0 enables context switching when an int0 interrupt occurs. clearing ic0 disables context switching for the int0 interrupt. nmic nmi context switching enable 0, r/w nmic is the context switching enable for nmi. setting nmic enables context switching when an nmi interrupt occurs. clearing nmic disables context switching for the nmi interrupt. 4.3.3 program and loop counters the pc (program counter) and lc (loop counter) are directly accessible 16-bit counters. the pc always contains the address of the next instruction to be executed. the lc register can be used as an index inside the block-repeat loop, or for determining the value of the block- repeat counter when a jump out of the block-repeat loop occurs. the block-repeat loop counter is a global register and can also serve as a 16-bit general purpose register. pc and lc clear to zero after reset.
4-16 registers 4.4 status registers three status registers hold the ?ags, status bits, control bits, user i/o bits, and paging bits for direct addressing. the contents of each register and their ?eld de?nitions are described in the following subsections. table 4.10 lists the status registers for the CWDSP1650. 4.4.1 status register 0 (st0) figure 4.9 shows the ?elds within status register 0. each ?eld is described below. the ?ags (z, m, n, v, c, e, and l) indicate the result of the last alu, bfo, or barrel shifter output operation. when one of these outputs is latched into a destination accumulator, the ?ags normally indicate that accumulator status. all bits in this register are read/write and clear during a processor reset. figure 4.9 status register 0 (st0) a0e accumulator 0 extension [15:12], r/w this ?eld contains the contents of the accumulator 0 extension after an operation that used accumulator 0 as a destination. z zero flag 11, r/w the zero flag is set if the alu, bfo, or barrel shifter output used at the last instruction equals zero. the zero ?ag also indicates the result of the test bit instructions (tst0, tst1, or tstb). table 4.10 status registers register abbreviations page status register 0 st0 4-16 status register 1 st1 4-18 status register 2 st2 4-19 15 1211109876543210 a0e z m n v c e l r im1 im0 ie sat
status registers 4-17 m minus flag 10, r/w the minus flag is set if the alu, bfo, or barrel shifter output used at the last instruction is a negative number; and cleared otherwise. the minus ?ag is identical to the most-signi?cant bit of the output (bit 35). n normalized flag 9, r/w the normalized flag is set if the least-signi?cant 32 bits of the alu or barrel shifter output used at the last instruction are normalized; cleared otherwise. in other words, n is set if: z {(bit 31 ? bit 30) ? e} v over?ow flag 8, r/w the over?ow flag is set if an arithmetic over?ow (36-bit over?ow) occurs after an arithmetic operation, and is cleared otherwise. the over?ow ?ag indicates that the result of an operation cannot be represented in 36 bits. c carry flag 7, r/w the carry flag is set if the result of an add generates a carry, or if the result of a subtract generates a borrow; it is cleared otherwise. the carry ?ag also re?ects the rotated bit, or the last bit shifted out of the 36-bit result. e extension flag 6, r/w the extension flag is set if bits [35:31] of the alu or barrel shifter output used at the last instruction are not identical; otherwise it is cleared. clearing the extension ?ag indicates that the four most-signi?cant bits of the output are sign extensions of bit 31 and can be ignored. l limit flag 5, r/w the limit flag has two functions: to latch the over?ow ?ag, and to indicate limitation during accumulator move or lim operations. the l bit is set if the over?ow ?ag is set or if a limitation occurs either when an accumulator move instruction (mov or push) through the data bus is used, or when a limitation occurs when the lim instruction executes. otherwise, l is not affected. r rn register is zero flag 4, r/w the r ?ag is set if the result of an rn modi?cation operation (rn; rn+1; rn-1; rn+s) is zero. only the modr and norm instructions affect this ?ag. the r ?ag
4-18 registers status remains unchanged until one of the above instructions is used. im1 interrupt 1 mask 3, r/w im1 is the interrupt mask for int1. clearing im1 to zero disables the interrupt, setting im1 to one enables the interrupt. im0 interrupt 0 mask 2, r/w im0 is the interrupt mask for int0. clearing im0 to zero disables the interrupt, setting im0 to one enables the interrupt. ie interrupt enable 1, r/w clearing ie to zero disables all maskable interrupts, setting ie to one enables all maskable interrupts. to modify the interrupt enable bit, use the instructions eint (enable interrupts) or dint (disable interrupts). sat saturation mode disable 0, r/w clearing sat to zero enables saturation mode when the contents of the accumulator are transferred to the data bus. setting sat to one disables the saturation mode. note: the sat bit values have no affect on the lim instruction operation. 4.4.2 status register 1 (st1) figure 4.10 shows the ?elds within status register 1. each bit ?eld of st1 is described below. all bits clear to zero after reset. figure 4.10 status register 1 (st1) a1e accumulator 1 extension [15:12], r/w this ?eld contains the contents of the accumulator 1 extension after an operation that used accumulator 1 as a destination. ps product shifter control [11:10], r/w the ps bits determine the scaling shift of the p register output. writing to the st1 register modi?es the ps bits. 15 12 11 10 9 8 7 0 a1e ps res page
status registers 4-19 the ps bits control whether the product is shifted right by one, left by one, left by two, or is not shifted. res reserved [9:8] these bits are reserved for lsi logic. these bits always read as ones and are not affected when written. page data memory space page [7:0], r/w in direct address mode, these bits address the data memory page. pages are addressed in 128-byte increments. see section 3.3.1.1, short direct addressing, for more information on direct addressing. to modify these bits, either write to the st1 register, use the load instruction, or use the lpg instruction. 4.4.3 status register 2 (st2) figure 4.11 shows the ?elds within status register 2. each ?eld is described below. figure 4.11 status register 2 (st2) ip1 interrupt pending 1 15, r ip1 is the interrupt pending bit for the int1 interrupt. ip1 is set when the int1 interrupt is active. ip1 re?ects the interrupt level regardless of the mask bit. ip0 interrupt pending 0 14, r ip0 is the interrupt pending bit for the int0 interrupt. ip0 is set when the int0 interrupt is active. ip0 re?ects the interrupt level regardless of the mask bit. ps number of shifts 0 0 no shift 0 1 shift right by one 1 0 shift left by one 1 1 shift left by two 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ip1 ip0 ip2 res iu1 iu0 ou1 ou0 s im2 m5 m4 m3 m2 m1 m0
4-20 registers ip2 interrupt pending 2 13, r ip2 is the interrupt pending bit for the int2 interrupt. ip2 is set when the int2 interrupt is active. ip2 re?ects the interrupt level regardless of the mask bit. res reserved 12 this bit is reserved for lsi logic. it reads as one and is not affected when written. iu1 user-de?ned input 1 11, r iu1 reflects the state of the core input user-defined input 1. iu0 user-de?ned input 0 10, r iu0 reflects the state of the core input user-defined input 0. ou1 user-de?ned output 1 9, r/w ou1 determines the state of the core output user- de?ned output 1. processor reset clears ou1 to zero. ou0 user-de?ned output 0 8, r/w ou0 determines the state of the core output user- de?ned output 0. processor reset clears ou0 to zero. s shift mode 7, r/w this bit determines the shift method for all of the shift instructions: shfc, shfi, moda, modb, movs, and movsi. if s is cleared to zero, the shift instruction is an arithmetic shift. if s is set to one, the shift instruction is a logical shift. processor reset clears the shift mode bit to zero. im2 interrupt 2 mask 6, r/w im2 is the interrupt mask for the int2 signal. clearing im2 to zero disables int2; setting im2 to one enables int2. this bit is cleared to zero during processor reset. mn modulo enable [5:0], r/w setting an mn bit to one enables modulo addressing for the corresponding rn register, as speci?ed by the mod s shift instruction 0 arithmetic shift 1 logical shift
user-de?ned registers 4-21 and step values in the relevant cfg register. processor reset clears the mn bits. note: the modr instruction is the only instruction that can use one of the rn registers without being affected by the corresponding mn bit. the modr instruction has an option that disables modulo operation. see chapter 7, instruction set, for more information. 4.5 user-de?ned registers the CWDSP1650 supports four user-de?ned registers that enable expansion of the core in off-core glue logic. the 16-bit user-de?ned registers are part of the core register list, which means they can be accessed by most of the CWDSP1650 instructions. the core does not provide a direct mechanism to clear the user-de?ned registers after reset. modulo enable bit address register m5 r5 m4 r4 m3 r3 m2 r2 m1 r1 m0 r0
4-22 registers
5-1 chapter 5 signals this chapter describes the CWDSP1650 interfaces to logic external to the core. it contains the following subsections: section 5.1, logic symbol section 5.2, bus interface section 5.3, program control interface section 5.4, off-core data memory interface section 5.5, user-de?ned register interface section 5.6, emulation and trace buffer interface section 5.7, processor control interface section 5.8, scanice control interface section 5.9, clock control interface in the descriptions that follow, the verb assert means to drive true or active. the verb deassert means to drive false or inactive. 5.1 logic symbol figure 5.1 shows the logic symbol for the CWDSP1650 dsp core.
5-2 signals figure 5.1 CWDSP1650 logic symbol iack_int0 iack_int1 iack_int2 iack_nmi int0 int1 int2 iu0, iu1 nmi oak_intmode ou0, ou1 movp_flag edb[15:0] idb[15:0] iab[15:0] pren pwen rd_ext_reg sel_ext_reg_rd[1:0] sel_ext_reg_wt[1:0] bi blockloop bti_service dvm iack_bi emulation processor program CWDSP1650 rst control user-de?ned clock mem_cfg[2:0] xdb[15:0] xab[15:0] xren xwen ydb[15:0] yab[15:0] yren ywen branching clr_istat control interface register interface ext_in[15:0] ld_ext_reg invalid_pa int_seen sel_trace[1:0] trace_unwrite trace_write mvd_exec trace_tag trap_service and trace buffer interface scan_out scan_ws scan_en scan_in test control interface wait_ctl core_clk icu_clk mclk scanice control interface interface bus interface off-core data memory interface ram_rd ram_wt
bus interface 5-3 5.2 bus interface the edb comprises the main bus for most data transactions. edb[15:0] external data bus output this unidirectional 16-bit data bus transfers data from the internal core components (pcu, daau, and so on) to the off-core components (yram, xram, pram, external registers, etc.) edb[15:0] is the external extension of the main data bus. 5.3 program control interface the following signals relate to program memory access. idb[15:0] program data bus input this 16-bit bus transfers both program instructions and program data to the core from the program memory. iab[15:0] program address bus output the core drives this 16-bit bus with the memory address of either the program instruction or the program data. pren program read enable output the core drives this signal high to request program data. pren remains active through the complete program request cycle, including all wait cycles. pwen program write enable output the core drives this signal high to indicate either a program word or a data word write to the program memory space through the external data bus. pwen remains active through the complete program write cycle, including all wait cycles.
5-4 signals 5.4 off-core data memory interface the following signals are used in data memory access. mem_cfg[2:0] memory con?guration input these signals determine memory mapping for the core system. the memory con?guration can range from an equal mix of 32 kword x-memory / 32 kword y-memory, to a 63.75 kword x-memory / 256 word y-memory distribution. ram_rd memory read indicator output the core drives this signal high to indicate that the instruction about to be decoded will request a read from either the x- or y-memory data. when a data memory read is in the critical path, ram_rd can provide a designer with early indication of a memory access. ram_wt memory write indicator output the core drives this signal high to indicate that the instruction about to be decoded will request a write to either the x- or y-memory data. when a data memory write is in the critical path, ram_rd can provide a designer with early indication of a memory access. xdb[15:0] x-memory data bus input this unidirectional 16-bit bus transfers data to the core from the x-memory space. mem_cfg [2:0] x-memory space y-memory space 000 32 k (0x0000-0x7fff) 32 k (0x8000-0xffff) 001 48 k (0x0000-0xbfff) 16 k (0xc000-0xffff) 010 56 k (0x0000-0xdfff) 8 k (0xe000-0xffff) 011 60 k (0x0000-0xefff) 4 k (0xf000-0xffff) 100 62 k (0x0000-0xf7ff) 2 k (0xf800-0xffff) 101 63 k (0x0000-0xfbff) 1 k (0xfc00-0xffff) 110 63.5 k (0x0000-0xfdff) 512 (0xfe00-0xffff) 111 63.75 k (0x0000-0xfeff) 256 (0xff00-0xffff)
off-core data memory interface 5-5 xab[15:0] x-memory address bus output the core drives this 16-bit bus with the x-memory space address. the available x-memory address range is speci?ed by the mem_cfg[2:0] signals. xren x-memory read enable output the core drives this signal high to request data from the x-memory address speci?ed by the xab signal. xren remains active throughout the complete x-memory request cycle, including all wait cycles. xwen x-memory write enable output the core drives this signal high to indicate a x-memory data write through the external data bus to the address speci?ed by xab. xwen remains active through the complete x-memory write cycle, including all wait cycles. ydb[15:0] y-memory data bus input this unidirectional 16-bit bus transfers data to the core from the y-memory space. yab[15:0] y-memory address bus output the core drives this 16-bit bus with the y-memory address. the available y-memory address range is speci?ed by the mem_cfg[2:0] signals. yren y-memory read enable output the core drives this signal high to request y-memory data from the address speci?ed by the yab signal. yren remains active throughout the complete y-memory read cycle, including all wait cycles. ywen y-memory write enable output the core drives this signal high to indicate a y-memory data write through the external data bus to the address speci?ed by yab. ywen remains active through the complete y-memory write cycle, including all wait cycles.
5-6 signals 5.5 user-de?ned register interface the following signals are used when implementing the optional user-de?ned registers. ext_in[15:0] external registers input data bus input this 16-bit bus transfers data from the user-de?ned external registers to the core. ld_ext_reg external register write enable output the core drives this signal high during an external register write cycle. rd_ext_reg external register read enable output the core drives this signal high during an external register read cycle. sel_ext_reg_rd[1:0] select external register for reading output the core drives these signals with the code of the external register that is the source operand of the external register read instruction. sel_ext_reg_wt[1:0] select external register for writing output the core drives these signals with the code of the external register that is the destination operand of the external register write instruction. sel_ext_reg_rd[1:0] external register 00 0 01 1 10 2 11 3 sel_ext_reg_wt[1:0] external register 00 0 01 1 10 2 11 3
emulation and trace buffer interface 5-7 5.6 emulation and trace buffer interface the following signals are used in conjunction with the on-chip emulation module (ocem) to implement debug functionality. see chapter 8, on- chip emulation module (ocem), for further information on the ocem. bi breakpoint interrupt input asserting this signal high causes the core to service the trap/bi interrupt service routine (vector address 0x0002.) blockloop block-repeat detected output the core drives this signal high whenever it detects a jump back to the ?rst instruction in a block-repeat loop. branching branch detected output the core drives this signal high whenever a branch-type instruction occurs during program execution (see chapter 8, on-chip emulation module (ocem), for further information). bti_service bi/trap service active output the core asserts this signal high to indicate the execution of a trap/bi service routine. bti_service remains active from the decode of address 0x0002 until the third cycle decode of either the retid or reti instruction at the end of the service routine. clr_istat clear interrupt status output the core asserts this signal high when it serves an interrupt. dvm data value match output the core asserts this signal high to indicate a match between the data of the dvm register and the value of edb[15:0]. iack_bi breakpoint interrupt acknowledge output the core asserts this signal high to acknowledge a breakpoint interrupt.
5-8 signals invalid_pa invalid program address output the core asserts this signal high whenever either an invalid data read or data write occurs with the program memory space. int_seen interrupt indication output the core asserts this signal high when an interrupt is pending, or if the core is in a noninterruptible state. mvd_exec move data-to-program detected output the core asserts this signal high after it executes a movd instruction. this operation could corrupt the program memory, so the ocem monitors this condition. sel_trace[1:0] select addresses for trace output the core drives these signals with the program address values selected to be written to the ocem trace buffer. trace_tag trace address tag output asserting this signal high indicates that the current program address is one of two addresses stored for certain nonsequential program ?ow operations. the core stores the value of trace_tag with the trace address values in the trace buffer. trace_unwrite unwrite last trace address output the core drives this signal high to unwrite the last trace address from the trace buffer. an unwrite capability is needed to erase a conditional branch trace buffer entry when the branch is not taken. trace_write trace write output the core drives this signal high to indicate a data write to the trace buffer. trap_service trap service indicator output the core drives this signal high when a software trap occurs.
processor control interface 5-9 5.7 processor control interface the following signals relate to program ?ow control, memory access cycle de?nition and interrupts: iack_int0 maskable interrupt 0 acknowledge output the core drives this signal high to acknowledge service to maskable interrupt 0. iack_int1 maskable interrupt 1 acknowledge output the core drives this signal high to acknowledge service to maskable interrupt 1. iack_int2 maskable interrupt 2 acknowledge output the core drives this signal high to acknowledge service to maskable interrupt 2. iack_nmi nonmaskable interrupt acknowledge output the core drives this signal high to acknowledge service to the nonmaskable interrupt. int0 maskable interrupt 0 request input asserting this signal high through external logic requests a core interrupt. this interrupt causes the core to serve the int0 interrupt service routine (vector address 0x0006), and can be internally masked by software. int0 must be synchronized with the rising edge of the main input clock. int1 maskable interrupt 1 request input asserting this signal high through external logic requests a core interrupt. this interrupt causes the core to serve the int1 interrupt service (vector address 0x000e), and can be internally masked by software. int1 must be synchronized with the rising edge of the main input clock. int2 maskable interrupt 2 request input asserting this signal high through external logic requests a core interrupt. this interrupt causes the core to serve the int2 interrupt service (vector address 0x0016), and can be internally masked by software. int2 must be synchronized with the rising edge of the main input clock.
5-10 signals iu1, iu0 user input pins input these signals are discrete inputs to the core and can be read by software as bits of status register 2. movp_flag privacy for the program code output the core asserts this signal high whenever it executes a movp instruction. an external memory controller can protect the on-chip program from unauthorized external reads by monitoring movp_flag. when movp_flag is asserted, the external memory controller checks if the access is authorized. if not, the controller disables that transaction enable, thereby protecting the program memory information. nmi nonmaskable interrupt request input asserting this signal high through external logic requests a core interrupt. this interrupt causes the core to serve the nmi service routine (vector address 0x0004), and cannot be internally masked by software. nmi must be synchronized with the rising edge of the main input clock. oak_intmode interrupt mode input this signal has been reserved for future enhancement. during CWDSP1650 operation, hold the oak_intmode signal low at all times. ou1, ou0 user output pins output these discrete control signals can be controlled by software. rst core reset input asserting this signal high resets the core. 5.8 scanice control interface the following signals are used in CWDSP1650 systems which implement the scanice debug system. scan_en scan enable input asserting this signal high con?gures internal registers for a serial scan.
clock control interface 5-11 scan_in scan chain input input this signal connects directly to the test input of the ?rst ?ip-?op in the kernel scan chain. scan_out scan chain output output this signal connects directly to the output of the last ?ip- ?op in the kernel scan-chain. scan_ws scan write strobe input asserting this signal high disables memory write enables from the core. disabling memory writes protects the contents of the off-core rams during the scan mode. test test mode input when scan_en is low, asserting test forces all kernel registers to be load enabled, implementing a capture function when in scan mode. asserting test also forces the multiplier input latches transparent so they can be controlled when in scan mode. test should be asserted whenever scan_en is asserted. 5.9 clock control interface these signals regulate the CWDSP1650 core clocking system. core_clk main clock output main clock that drives all CWDSP1650 modules, apart from the icu. icu_clk interrupt control unit clock output this signal is the controlling clock for the icu. mclk main input clock input this clock is the main input clock. wait_ctl wait request input asserting this signal high forces the core in a wait state mode. while wait_ctl is asserted, the core clock (core_clk) is held low. deasserting wait_ctl low for one full clock cycle ends this wait state mode. the core clock then begins generating clock pulses again at the rising edge trigger and the core can resume the current transaction.
5-12 signals
6-1 chapter 6 operation this chapter contains waveforms that depict core signals during various operations. these waveforms are intended to assist hardware designers in understanding the inter-relations of the core signals and how operations initiated on one interface propagate to others. this chapter is further divided into the following sections: section 6.1, reset section 6.2, boot procedure section 6.3, interrupts section 6.4, memory interface section 6.5, user-de?ned register interface section 6.6, program protection mechanism section 6.7, clock control unit (ccu) 6.1 reset reset is an external event used at any time to put the CWDSP1650 core into a known state. asserting the reset input (rst) high places the core into the reset state. the reset state causes the core to terminate all code execution and initialize (clear) all registers and status bits. deasserting rst causes program execution to start from location 0x0000. figure 6.1 shows a waveform for a reset operation.
6-2 operation figure 6.1 reset operation rst must be held asserted for at least six mclk cycles. during reset, the core drives the program address bus (iab) with all zeros and deasserts the program read enable (pren). after the core deasserts rst, it starts fetching instructions from program address 0x0000 on the next rising edge of core_clk. since the CWDSP1650 ccu synchronizes rst internally with mclk, mclk must not stop while rst is asserted. for details on the effect of rst on speci?c registers, see the descriptions in chapter 4, registers. 6.2 boot procedure the boot procedure allows automatic code downloading from an external device (for example, eprom or ram) to a ram device located in the program space. the boot procedure is not included in the CWDSP1650 core, but is implemented in the off-core bus interface unit (biu). boot support is transparent to the CWDSP1650 core. an off-core device may force a branch instruction onto the program data bus (idb) after reset to direct the core to a boot routine. the core fetches this branch instruction and executes it as if it was fetched from memory. subsequently, the core executes the boot routine to load the program code to the program memory. a boot routine should end by jumping to the program it downloaded. as an example, an off-core bus interface unit (biu) on the CWDSP1650 reference device samples a boot pin during deassertion of rst. if this off-core boot pin is valid, the biu forces the instruction brr #-3 onto the idb through a multiplexor. this causes the next instruction to be mclk core_clk rst iab[15:0] pren at least 6 cycles 0x0000
interrupts 6-3 fetched from address 0xfffe, the location where the boot routine is held in memory. inside the boot routine, the instruction movd can be used to download program code from a data memory (slow eprom or rom) to a ram device within the program space. figure 6.2 illustrates how to initiate the CWDSP1650 boot procedure. figure 6.2 entering boot mode 6.3 interrupts the CWDSP1650 core supports six different interrupts to handle exceptions: three hardware maskable interrupts (int0, int1, int2) one nonmaskable interrupt (nmi) two breakpoint interrupts (software/hardware) in one signal (bti_service) for use with the ocem the core can either program the registers st0 and st2 or use the eint and dint instructions to enable or disable maskable interrupts. an off-core device can use any of the hardware interrupts to request services from the core. a program can request system service using the trap instruction. after accepting an interrupt, the core suspends normal program execution and calls a service routine to handle the exception. each service routine starts from an address, known as the interrupt vector, brr - 3 0x0000 1 0xfffe 0xffff core_clk boot rst iab[15:0] pren idb[15:0] force onto idb with external boot logic
6-4 operation dedicated to that speci?c interrupt. the trap/bi interrupts share the same interrupt vector. the core acknowledges each hardware interrupt using a dedicated acknowledgment signal while it services that interrupt. after the exception has been handled, an interrupt service routine returns control to the interrupted program, which resumes execution from the suspended point of the program. note that the bi/trap vector is used by the on-chip emulation module (ocem) when using either the cdi or scanice debug. the remainder of this section is further divided into the following subsections: section 6.3.1, maskable interrupts section 6.3.2, nonmaskable interrupt (nmi) section 6.3.3, trap/bi interrupts section 6.3.4, interrupt protocol section 6.3.5, interrupt priority section 6.3.6, context switching section 6.3.7, interrupt nesting section 6.3.8, interruptible state 6.3.1 maskable interrupts int0, int1, and int2 are active high maskable interrupts. the core processes a maskable interrupt provided the following conditions are true: CWDSP1650 is in an interruptible state nmi or bti_service interrupts are not pending or currently being serviced interrupt enable bit (ie) in the st0 register is set to one corresponding interrupt mask bit (imn) in the st0 and st2 registers is set to one
interrupts 6-5 table 6.1 lists the bits and signals associated with the maskable interrupts. each maskable interrupt is masked independently by clearing to zero one of the mask bits im0, im1, or im2. clearing the ie bit in the st0 register disables all maskable interrupts. always use the instruction eint and dint to manipulate the ie bit when enabling and disabling maskable interrupts explicitly. when the core services a maskable interrupt, it clears the ie bit to disable all other maskable interrupts. the interrupt mask bits are unaffected. pending maskable interrupts are serviced only after the ie bit is set to one. the core acknowledges the pending maskable interrupt through one of the iack_intn signals. to return from a maskable interrupt service routine, one of the four instructions reti, retid, ret, or retd can be used. the instructions reti and retid set the ie bit, allowing pending maskable interrupts to be serviced. the ret and retd instructions do not affect the ie bit. interrupt priority arbitrates between simultaneous maskable interrupts. among the maskable interrupts, int0 has the highest priority and int2 has the lowest. the priority between int0, int1, and int2 is signi?cant only if more than one interrupt is received at the same time and the ie bit is set to one. in these cases, the core services the interrupts according to their priorities. nesting of maskable interrupts is supported only if enabled by the service routine. when enabled, any maskable interrupt can interrupt the service routine. interrupt priority does not affect nesting of maskable interrupts. an nmi or trap/bi interrupt can always interrupt a maskable interrupt service routine, regardless of the ie bit. the core sets the ip0, ip1, or table 6.1 maskable interrupt bits and signals interrupt signal interrupt acknowledge signal interrupt enable bit interrupt mask bit interrupt pending bit int0 iack_int0 ie (st0) im0 (st0) ip0 (st2) int1 iack_int1 ie (st0) im1 (st0) ip1 (st2) int2 iack_int2 ie (st0) im2 (st2) ip2 (st2)
6-6 operation ip2 bit in st2 register once the corresponding interrupt int0, int1, or int2 has been asserted, even when they are masked and/or disabled. these bits can be used to poll the interrupt status. 6.3.2 nonmaskable interrupt (nmi) nmi is a nonmaskable interrupt that cannot be masked or disabled under software control. the core accepts nmi when it is in an interruptible state and is not already servicing either an nmi or a trap/bi request. when servicing an nmi, the core acknowledges the interrupt with the iack_nmi signal. while the core is servicing an nmi, all incoming maskable interrupts are held pending. only a trap/bi request can interrupt an nmi service routine. an nmi service routine must return with a reti or retid instruction to clear the interrupt logic internal to the core. the ie bit in status register st0 is not affected by servicing an nmi interrupt. 6.3.3 trap/bi interrupts trap is a software interrupt and is the only interrupt that can be activated directly by a software instruction. bi is a hardware breakpoint interrupt that activates when the bi core input is asserted. the ocem uses the bi interrupt to provide emulation capability within the core. the core handles the bi and trap interrupts almost identically and both share the same interrupt vector. the core takes the following actions in addition to the normal interrupt protocol when servicing a bi/trap interrupt: the program counter is stored into the data value match register (pc ? dvm.) the core asserts the trap/bi active indicator (bti_service) high throughout the service routine. for trap interrupt, the core asserts the software trap indicator (trap_service) high throughout the service routine to indicate that a software trap occurred. the core cannot disable or mask a trap/bi interrupt under software control. it always services a requested trap/bi interrupt when it is in an interruptible state and is not already servicing this interrupt. while the
interrupts 6-7 core is executing the trap/bi service routine, it disables servicing of all other hardware interrupts (nmi, int0, int1, and int2). nesting of bi/trap interrupts is not allowed; it is illegal to use a trap instruction in a trap/bi service routine. a trap/bi service routine must end with an reti or retid instruction to clear the interrupt logic internal to the core. the ie bit in status register st0 is not affected by servicing a trap/bi interrupt. the trap_service output signal differentiates between a trap (asserted high) or a bi (deasserted low) interrupt. if required, a service routine can differentiate between a trap and a bi interrupt only with the assistance of external glue logic that latches the signal. for more information on the trap or bi service see the section 8.3, ocem signals. 6.3.4 interrupt protocol the CWDSP1650 de?nes an interrupt protocol to avoid race hazards due to the asynchronous nature of external interrupts. figure 6.3 illustrates this interrupt protocol. figure 6.3 interrupt protocol the core registers interrupts internally on the rising edge of icu_clk. the maskable interrupts (int0, int1, and int2) are registered even when disabled, but are not registered when masked. see section 6.3.1, maskable interrupts, for further details of masking and disabling the maskable interrupts. a registered interrupt is cleared only when the core services the interrupt or during a core reset. icu_clk intn 1 clr_istat iackn 2 iab return addr ivec 1. intn can be int2, int1, int0, nmi, or bi. 2. iackn can be iack, int2, iack_int1, iack_int0, iack_nmi or iack_bi.
6-8 operation an on-core priority encoder selects the highest priority interrupt to be serviced when multiple interrupts simultaneously arrive. a lower priority interrupt is kept pending and is serviced only when all higher priority interrupts have been serviced. see section 6.3.5, interrupt priority, for more information about interrupt priority servicing. when the core is in an interruptible state, it starts servicing the highest priority registered interrupt at the start of an instruction decode cycle (see section 6.3.8, interruptible state, for further details). instead of decoding the prefetched instruction, the core passes a pseudo- instruction to the instruction decoder to direct the core to the appropriate service routine. as shown in figure 6.3 , the core performs the following operations on the decode cycle of the pseudo-instruction: the vector address of the interrupt being serviced is forced onto iab to initiate prefetching of the ?rst instruction in the corresponding service routine (ivec ? iab.) assert clr_istat for one cycle to clear the internal ?nite state machine inside the core (clr_istat high.) complete execution of the instruction already decoded and in the operand fetch stage of the processor pipeline. save the return address by pushing the address of the last prefetched instruction onto the system software stack (pc ? (sp), then sp - 1 ? sp.) during the execution cycle of the interrupt pseudo-instruction, the core asserts the corresponding acknowledgment signal (iackn). iackn clears only after the corresponding interrupt is deasserted. hence, a hardware interrupt signal should be held until the core acknowledges it (iackn high.) note: when servicing a hardware interrupt, the core clears its internal interrupt logic only when the interrupt is deasserted. to comply with the interrupt protocol, a hardware interrupt request should be held asserted until the core acknowledges it. after that, the request must be deasserted before another request is raised on the same interrupt input. otherwise, the core ignores this constantly asserted interrupt after servicing it once.
interrupts 6-9 6.3.5 interrupt priority the CWDSP1650 core prioritizes interrupts when more than one interrupt request is simultaneously raised. table 6.2 lists all the interrupts supported by the core in the descending order of their priorities. their vector addresses and acknowledgment signals are also listed in the table. the core services the highest priority interrupt it registered while the others are held pending. the core services an interrupt only when no higher priority interrupt needs attention. a higher priority interrupt that arrives late is serviced ?rst even if a lower priority interrupt has already been held pending but not yet serviced. 6.3.6 context switching when servicing an interrupt, the service routine has to save the contents of any registers it uses before writing to them. before returning, the service routine should restore these registers with the saved values so that the interrupted program can resume in the correct context. to reduce the overhead involved, the CWDSP1650 supports automatic context switching for the nmi and intn interrupts. automatic context switching on an interrupt is enabled by setting the nmic and icn bits in the icr register. see section 4.3.2, internal con?guration register (icr), for more information. when enabled, the core performs the following operations automatically with zero overhead before executing the interrupt service routine: table 6.2 interrupts and priorities interrupt acknowledge vector priority trap/bi iack_bi 0x0002 1 nmi iack_nmi 0x0004 2 int0 iack_int0 0x0006 3 int1 iack_int1 0x000e 4 int2 iack_int2 0x0016 5
6-10 operation push st0[0], st0[11:2], st1[11:10], and st2[7:0] to their shadow registers. the saved status register bits preserve the interrupted program status. swap the page bits of the st1 register with its shadow register. the swapped page bits allow a service routine to have instant access to a data memory page reserved for interrupt servicing. swap the a1 and b1 accumulators. this makes it convenient to reserve b1 for interrupt servicing. automatic restoration of the switched context can be performed when returning from the interrupt service routine using the reti instruction. an interrupt service routine has to explicitly save and restore any register it uses not preserved by the above operations. the context switching mechanism can also be activated by executing the cntx instruction. the shadow page bits are not directly accessible by software, but have to be explicitly selected with the cntx instruction. see section 4.1.3, interrupt context switching registers, for more information about context switching. banke is another useful instruction for context saving and restoration. it can swap up to four of the following pairs of registers in one cycle: r0 ? r0b r1 ? r1b r4 ? r4b cfgi ? cfgib for more detailed information about the reti, cntx, or banke instructions, see chapter 7, instruction set. 6.3.7 interrupt nesting the CWDSP1650 also supports interrupt nesting. in general, an interrupt service routine can be interrupted only by a higher priority interrupt. the lower priority interrupt service routine resumes execution after the higher priority interrupt has been serviced. when servicing a maskable interrupt (intn), the core clears the ie bit in status register st0 to disable servicing any further maskable interrupts. a reti or retid instruction at the end of a maskable interrupt service routine sets the ie bit to re-enable the maskable interrupts. nesting maskable interrupts can be
interrupts 6-11 enabled inside a maskable interrupt service using the eint instruction to explicitly set the ie bit to one. when the ie bit is set, a maskable interrupt can interrupt any maskable interrupt service routine. the relative priorities of the maskable interrupts do not affect the nesting of any maskable interrupts. 6.3.8 interruptible state while the core is in a noninterruptible state, it will not service any of the interrupts, regardless of their priority. all interrupts received while the core is in a noninterruptible state are held pending. the core is in a noninterruptible state during: multicycle instruction executions wait states a nested repeat loop execution during reset, the core ignores any interrupt. if an interrupt is asserted when rst deasserts, the core services the interrupt after prefetching from location 0x0000. the core also becomes noninterruptible temporarily after executing some instructions. these cause a delay in servicing an interrupt. table 6.3 describes all cases in which interrupts are delayed due to a speci?c instruction execution. the second column lists the interrupt delays in machine cycles (core_clk cycles). core_clk can stretch to multiple-cycles in case of wait states (it stretches until the end of the wait interval.)
6-12 operation 6.4 memory interface the CWDSP1650 harvard architecture separates program memory and data memory spaces. the core further divides the data memory into two separate spaces, x and y, to increase memory bandwidth. table 6.4 shows how the core input mem_cfg[2:0] signals de?ne partitioning of the total 64 kwords of data memory space into the x- and y-data spaces. table 6.3 interrupt latency after speci?c instructions current instruction interrupt delay after the instruction interrupt 1 1. intn = int0, int1, int2. 2. soperand represents every source operand except for a ##long immediate first repetition of instruction during a repeat loop after returning from an interrupt one cycle intn, nmi enabling or unmasking interrupts with the following instructions: mov soperand, st0 movp (axl), st0 set/rst/chng/addv/subv/mov ##long immediate, st0 pop st0 one cycle int0, int1 unmasking interrupt with the following instructions: mov soperand, st2 movp (axl), st2 set/rst/chng/addv/subv/mov ##long immediate, st2 pop st2 one cycle int2 retd, retid, mov soperand, pc movp (axl), pc two cycles intn, nmi, bi mov ##long immediate, pc one cycle intn, nmi, bi
memory interface 6-13 the memory interface of the CWDSP1650 allows a ?exible selection of memory devices. only single-port memory is required, although dual or multiport memory can also be supported. there is no restriction on any sequence of read and write transactions on any of the memory spaces. the core has a single output bus but separate input buses and address buses for each memory space. all memory buses are 16-bits wide. the external data bus (edb) is the single output bus to all off-core devices including data memory, program memory and user-de?ned registers (see section 6.5, user-de?ned register interface, for more information.) the core indicates which device it is writing to by using dedicated write-enable signals. the core has three separate memory data input buses. the x-data bus (xdb) receives input from the x-data space, the y-data bus (ydb) receives input from the y-data space and the instruction data bus (idb) receives data and instructions from the program memory. the core uses dedicated read-enable signals to control which memory space or external register is read from. the core also has a separate address bus for each memory space. the x-address bus (xab) and y-address bus (yab) output addresses for the x- and y-data spaces respectively. the program address bus (iab) outputs program memory addresses. table 6.4 data memory space partitioning mem_cfg[2:0] x-memory size (16-bit words) y-memory size (16-bit words) 000 32 k 32 k 001 48 k 16 k 010 56 k 8 k 011 60 k 4 k 100 62 k 2 k 101 63 k 1 k 110 63.5 k 512 111 63.75 k 256
6-14 operation table 6.5 summaries the memory interface signals of the CWDSP1650. for more information about program and data memory, see chapter 3, data formats, memory and addressing. for program and data memory timing diagrams, see chapter 10, speci?cations. 6.4.1 memory interface with slow memory devices the core supports transactions with slow memory devices (in either program or data memory space) through a built-in wait state mechanism. the clock control unit (ccu) suspends core_clk to put the CWDSP1650 into a wait state when the core input wait_ctl is asserted high on the rising edge of mclk. the core remains in the wait state until the rising edge of mclk after wait_ctl is deasserted. this extends the machine cycle time to match the memory access time. during wait stated cycles most parts of the core are effectively put on hold. the interrupt control unit (icu) and the ccu are not clocked by core_clk and so are not affected. all output signals on the memory interfaces are kept stable throughout the wait states. note that for every machine cycle, the core can fetch from several off-core devices concurrently. these include program memory, x-data memory, y-data memory and the user-de?ned registers. a wait state request must insert enough wait states to allow enough time for the slowest accessed device. for example, suppose that the program space is composed of a fast memory device (zero wait states) and a slow memory device (three wait states). the data space is composed of a fast memory device (zero wait states) and a slow device (four wait states). for this example, table 6.6 summarizes the wait interval for four cases in which the program and data memories are fetched simultaneously. table 6.5 memory signals interface memory space output bus input bus address bus write control read control x data edb xdb xab xwen xren y data edb ydb yab ywen yren program edb idb iab pwen pren
user-de?ned register interface 6-15 for more information about wait state timing and diagrams, see chapter 10, speci?cations. 6.5 user-de?ned register interface the CWDSP1650 core architecture supports up to four user-de?ned registers. these user-de?ned registers enable expansion of the core in off-core logic. these 16-bit user-de?ned registers are considered part of the core register list and can be accessed directly by most CWDSP1650 instructions. the core reads and writes the user-de?ned registers using a dedicated interface. when writing to user-de?ned registers, the core asserts the output signal ld_ext_reg and speci?es the destination with the 2-bit output sel_ext_reg_wt. the core outputs the data to the de?ned registers through the edb bus. when reading from the user-de?ned registers, the core asserts the output signal rd_ext_reg and speci?es the source with the 2-bit output sel_ext_reg_rd. the core reads the data through the ext_in[15:0] bus. table 6.6 example for de?ning the number of wait cycles transaction type wait interval (cycles) program fast (0 cycles) with data fast (0 cycles) 0 program slow (3 cycles) with data fast (0 cycles) 3 program fast (0 cycles) with data slow (4 cycles) 4 program slow (3 cycles) with data slow (4 cycles) 4
6-16 operation table 6.7 shows the code (either on sel_ext_reg_wt or sel_ext_reg_rd) associated with each user-de?ned register. the user-de?ned register transactions can have wait states as in the memory transactions. once a wait state occurs (wait_ctl is asserted), the user-de?ned register interface is held valid throughout the extended access cycle. if a design has a destructive read or a destructive write, where the read or the write operation causes an internal mechanism to be initiated, the read or write must be blocked appropriately by using wait_ctl. otherwise, multiple read/write triggers during the wait interval may cause register data to be lost or corrupted. for more information about user-de?ned register timing and diagrams, see chapter 10, speci?cations. 6.6 program protection mechanism the program protection mechanism protects the user program from unauthorized reading. it prevents infringement on intellectual property rights by reverse engineering of the program code held in on-chip memory. the CWDSP1650 core supports program protection by asserting the movp_flag signal when executing a movp instruction. the movp instruction is the only instruction that can read from the program memory space and write the data obtained to the data memory space. an off-core device, typically a biu, can use movp_flag to gate the program memory read-enable signal. the protection logic detects any unauthorized reads and prevents the program memory from being read. table 6.7 user-de?ned register coding user-de?ned register code ext0 00 ext1 01 ext2 10 ext3 11
clock control unit (ccu) 6-17 figure 6.4 shows how to protect the lower 32 kwords of the program space in an application which maps this space to on-chip rom. figure 6.4 memory protection mechanism off-chip memory mapped to the upper 32 kwords of program space can be modi?ed to insert a routine that copies on-chip program code to another off-chip data memory. this can help where effective access control is dif?cult, if not impossible. to prevent such an intrusion, a biu can detect the execution of a movp instruction fetched from off-chip memory using the movp_flag and iab[15]. when detected, the biu stops the core pren signal from reaching the CWDSP1650 reference device output-enable (oe) pin of the on-chip program memory. 6.7 clock control unit (ccu) the CWDSP1650 clock control unit (ccu) is a module external to the core, available as an optimized hard-macro. the ccu provides ?exible movp core_clk iab[15:0] idb pren movp_flag oe
6-18 operation control of the clock speed and sources for the core and surrounding peripherals. table 6.8 lists the ccu output clocks. 6.7.1 ccu operation the ccu derives its output clocks from either the master clock or scan_clk (the scanice interface generates start_scan after a breakpoint in scanice mode.) a clock control register provides software or system control over the clocks generated by the ccu. by writing appropriate values to the clock control register, the frequency of the clocks can be varied, the clocks can be stopped pending a restart by an interrupt, or scan_clk can be selected. see section 6.7.2, ccu register, for more information. wait states are controlled using the wait_ctl signal. when wait_ctl is asserted high, it suppresses the rising edge of core_clk. core_clk stays low until the wait_ctl signal is deasserted, after which core_clk follows the rising edge of icu_clk. core_clk also restarts when the core receives any unmasked interrupt. the restarted table 6.8 ccu output clocks clock description aligned clocks wait states stop mode core_clk in normal mode, this clock is a division of master clock. in scan mode, it switches to scan_clk. C yes yes icu_clk the icu registers interrupts using this clock. icu_clk is a skewed version of core_clk. Cnono ocem_clk a copy of core_clk. this is the reference clock for the ocem. core_clk yes yes pmem_clk a copy of core_clk that is skewed opti- mally for clocking synchronous program memory. C yes yes dmem_clk a copy of core_clk skewed optimally for clocking synchronous data memory. dmem_clk is only active during a data memory access. dmem_clk skew is pro- grammed through the skew bits in the ccu register. C yes yes
clock control unit (ccu) 6-19 core_clk frequency depends upon the restore value programmed into the ccu register. setting the ccu register stop bit to one initiates the clock stop mode. in stop mode, the core_clk signal is stopped, but icu_clk continues to run. when programming the ccu to enter stop mode, the interrupts must be disabled and re-enabled around the instruction that sets the stop bit in the ccu register using dint and eint instructions. three nop instructions should also be placed following the eint instruction, for example: mov ##0xf7e5, r0 ; set up ccu reg addr in r0 dint ; disable interrupts chng ##0x0010, (r0) ; set stop bit to one eint ; enable interrupts nop nop nop 6.7.2 ccu register figure 6.5 shows the ccu register and bit ?elds. figure 6.5 ccu register skew data memory clock skew bits [15:9], r/w the skew bits set the skew for dmem_clk. these bits should not normally be adjusted during operation since they directly affect memory access interface timings. the following table lists the skew values available through the skew bits. 15 9 8 5 4 3 0 skew rsv stop select skew bits read access (ns) write access (ns) 1000 2.00 6.50 1001 2.25 6.25 1010 2.50 6.50 1011 2.65 6.65 1100 2.80 6.80 1110 3.10 7.10 1111 3.25 7.25 0000 1 3.40 7.40
6-20 operation rsv restore value [8:5], r/w when the stop bit clears to zero, the ccu transfers the rsv value into the select bits of the clock control register. this allows the core to be put into a low-power idle state with the icu sampling interrupts at the selected slow clock rate. when the core receives an interrupt, it restarts at the clock rate determined by rsv and then responds to the interrupt. stop stop scan bit 4, r/w the ccu enters stop mode when this bit is set to one. in the stop mode core_clk is stopped, but icu_clk clocks are still running. this allows the icu to remain functional while the core is effectively stopped. any interrupt allowed through the icu clears the stop bit and restarts the core_clk. select select clock division [3:0], r/w this four-bit value selects which division of the master clock generates the output clocks. the master clock is divided by 2 (select) , so the output clock can be equal to master when select is 0x0, or divided by 16384 when select is 0xe. when select is 0xf, scan_clock is selected (this selection is reserved for use by the debug 0001 3.55 7.55 0010 3.70 7.70 0011 3.85 7.85 0100 4.00 8.00 0101 4.25 8.25 0110 4.50 8.50 0111 5.00 9.00 1. value after reset. skew bits read access (ns) write access (ns)
clock control unit (ccu) 6-21 system and should not be directly used in application software). select value output clock 0x0 master 0x1 master / 2 0x2 master / 4 . . . . . . 0xe master / 16384 0xf scan_clk
6-22 operation
7-1 chapter 7 instruction set this chapter describes the core instruction set, contains a complete alphabetical listing of all instructions, and is composed of the following sections: section 7.1, notations section 7.2, conventions and general information section 7.3, instruction functional groups section 7.4, instruction set list section 7.5, instruction opcode bit coding 7.1 notations this section de?nes the special symbols and notations used throughout this chapter. the areas with special notations include registers, numbers, data and program operands, and ?ags. 7.1.1 register notations table 7.1 de?nes the notations used to describe the core registers. table 7.1 register notations notations register rn address registers: r0, r1, r2, r3, r4, r5 ri address registers: r0, r1, r2, r3 rj address registers: r4, r5 (sheet 1 of 2)
7-2 instruction set ax a0 or a1 axl a-accumulator-low (lsp), x = 0, 1 axh a-accumulator-high (msp), x = 0, 1 axe a-accumulator extension, x = 0, 1 bx b0 or b1 bxl b-accumulator-low (lsp), x = 0, 1 bxh b-accumulator-high (msp), x = 0, 1 ac a0, a1, a0h, a1h, a0l, a1l bc b0, b1, b0h, b1h, b0l, b1l ab a0, a1, b0, b1 cfgx con?guration registers of daau (modi or modj, stepi or stepj), x = i, j sv shift value register sp stack pointer pc program counter lc loop counter (of block repeat) extx external registers, x = 0, 1, 2, 3 (user de?nable registers) reg a0, a1, a0h, a1h, a0l, a1l, b0, b1, b0h, b1h, b0l, b1l, r0, r1, r2, r3, r4, r5, rb, y, p, ph, sv, sp, pc, lc, st0, st1, st2, cfgi, cfgj, ext0, ext1, ext2, ext3 x x (multiplier input) register mixp minimum/maximum pointer icr internal con?guration register repc repeat counter dvm data value match register table 7.1 register notations (cont.) notations register (sheet 2 of 2)
notations 7-3 7.1.2 number representation binary numbers are initiated with either 0b or 0b. hexadecimal numbers are initiated with either 0x or 0x. 7.1.3 data and program operands table 7.2 and table 7.3 list the following information for the program and the data operands: number of bits operand range including the assembler mnemonics an operand example note that negative numbers can be written as four hexadecimal digits. for example, -0x80 can be written as 0xff80, and -0x20 can be written as 0xffe0. table 7.2 program operand notation operand number of bits assembler syntax example decimal hexadecimal binary direct address unsigned 8 bits (offset in page) 0C255 0x0C0xff 0b0000000C 0b11111111 add 120, a1 [##direct address] unsigned 16 bits 0C65535 0x0C0xffff 0b0C 0b1111111111 sub [##var1], a0 address unsigned 16 bits 0C65535 0x0C0xffff 0b0C 0b1111111111 call 0x5000
7-4 instruction set table 7.3 data operand notation operand number of bits assembler syntax example decimal hexadecimal binary # signed short immediate 8 (2s complement) # -128C127 # -0x80C0x7f # -0b1000.0000 C0b0111.1111 mov #-12, r0 # signed 6 bit immediate 16 (2s complement) # -32C31 # -0x20C0x1f # -0b100000C 0b011111 sh? b0, a0, #-4 # signed 5 bit immediate 5 (2s complement) # -16C15 # -0x10C0xf # -0b10000C 0b01111 movsi r1, a0, #3 # unsigned 9 bit immediate 9 (unsigned) # 0C511 # 0x0C0x1ff # 0b0000000C 0b1111.11111 load #270, modi # unsigned short immediate 8 (unsigned) # 0C255 # 0x0C0xff # 0b0000000C 0b11111111 add #0b10, a0 # unsigned 7 bit immediate 7 (unsigned) # 0C127 # 0x0C0x7f # 0b0000000C 0b01111111 load #3, stepj # unsigned 5 bit immediate 5 (unsigned) # 0C31 # 0x0C0x1f # 0b00000C 0b011111 mov #0x5, icr # unsigned 2 bit immediate 2 (unsigned) # 0C3 # 0x0C0x3 # 0b00C0b11 load #0b11, ps # bit number 4 (unsigned) # 0C15 # 0x0C0xf # 0b0000C 0b01111 tstb r0, #12 ## long immediate 16 (2s complement) ## -32768C 32767 ## -0x8000C 0x7fff ## -0b100000C 0b01111111 mov ## -0x9000, a0 ## offset 16 (unsigned) ## 0C65535 ## 0x0C 0xffff ## 0b0C 0b1111111111 mov ## 0xf000, r0 # offset7 7 (2s complement) -64C63 -0x40C0x3f -0b1000000C 0b0111111 add (rb-5), a1
notations 7-5 7.1.4 option fields the option ?elds contain the notations listed in table 7.4 . 7.1.5 condition field (cond) notations table 7.5 shows the notations for the condition ?eld. table 7.4 option field notations notations description eu extension unaffected. this ?eld is optional in the mov direct address, axh, [eu] instruction. when eu is mentioned, the data is transferred into axh without affecting axe. when eu is not men- tioned, the data is transferred into axh with sign-extension into axe. context context switching. this ?eld is optional in the reti instruction. when context is used, automatic context switching occurs. when context is not used, there is no context switching. dmod disable modulo. this ?eld is optional in the modr instruction. when dmod is mentioned, the rn is postmodi?ed with modulo modi?er disabled. when not mentioned, the mn bit in?uences the postmodi?cation of rn. table 7.5 condition field notations mnemonics description condition true always C eq equal to zero z = 1 neq not equal to zero z = 0 gt greater than zero m=0 ? z=0 ge greater or equal to zero m = 0 lt less than zero m = 1 le less or equal to zero m=1 z=1 nn normalize ?ag is cleared n = 0 v over?ow ?ag is set v = 1 c carry ?ag is set c = 1 (sheet 1 of 2)
7-6 instruction set 7.1.6 flag notations the eight ?ags are found in status register 0. there are eight ?ags: z, m, n, v, c, e, l, and r. the ?ags are depicted as shown below. flags that are affected by the speci?c instruction are shaded. flags that are not affected are not shaded. for full de?nitions and descriptions of the ?ag bits, see section 4.4.1, status register 0 (st0). 7.1.7 miscellaneous notations table 7.6 lists all other notations. e extension ?ag is set e = 1 l limit ?ag is set l = 1 nr r ?ag is cleared r = 0 niu0 input user pin 0, iuser0, is cleared C iu0 input user pin 0, iuser0, is set C iu1 input user pin 1, iuser1, is set C table 7.5 condition field notations (cont.) mnemonics description condition (sheet 2 of 2) 15 1211109876543210 status register 0 a0e z m n v c e l r im1 im0 ie sat table 7.6 miscellaneous notations notation description (x) the contents of x | one of the options should be included [ ] optional ?eld at the instruction speci?c notes (sheet 1 of 2)
conventions and general information 7-7 7.2 conventions and general information the conventions used through the instruction set are: 1. the arithmetic operations are performed in twos complement. 2. the following instructions allow postmodi?cation of the rn registers: C instructions that use indirect addressing mode C modr C norm C max, maxd, min (use r0 only) in these instructions, the contents of the rn register are postmodi?ed through the following: C instruction-controlled options C rn, rn + 1, rn C 1, rn + step C con?guration register (cfgi or cfgj) controlled options step size: stepi, stepj - 2s complement 7 bits (-64 to 63) modulo size: modi, modj - unsigned 9 bits (1 to 512) -> is assigned to >> shift right << shift left exp(x) exponent of x _ not ?or ? and table 7.6 miscellaneous notations (cont.) notation description (sheet 2 of 2)
7-8 instruction set C status register st2 controlled options for each rn register, it should be de?ned if modulo is enabled or disabled. when using modi or modj, the relative mn bit must be set. the only exception is with the modr instruction, which has an optional ?eld for disabling the modulo. for more details on the modulo arithmetic unit, see the subsection entitled modulo modi?cation on page 2-21. whenever the operand ?eld in the instruction is (rn), the rn can be postmodi?ed in one of the following four options. assembler syntax: (rn), (rn)+, (rn)-, (rn) + s four examples of instructions with postmodi?ed rns are: mov (r0)-, r1 mac (r4)+, (r0)+s, a0 add (r2), a1 modr (r5)- 3. the direct addressing mode assembler syntax is as follows: C the syntax when a one-word instruction is used is either direct address or [direct address]. (this instruction uses the contents of the page bits.) C the syntax when a two-word instruction is usedeven if the address is an eight-bit valueis [## direct address]. 4. the 16 most-signi?cant bits of the p register (denoted as ph) are write only. the 32-bit p register is updated after a multiply operation. the only way to read the p register is to transfer its contents into the ax accumulators or set the p register as an operand for an arithmetic and logic operation. the contents of the p register are sign-extended to 36 bits when transferred into the accumulator. this method allows you to store and restore the p register. 5. the p register is used as a source operand for different instructions as follows: C as one of the reg registers, Cina moda instruction pacr function, C in multiply instructions where the p register is added or subtracted from one of the accumulators.
conventions and general information 7-9 when the p register is used as a source operand, it is referred to as the shifted p register. shifted p register means that the p register is sign-extended into 36 bits and then shifted as de?ned by the ps ?eld in status register st1. in a right shift, the sign is extended; whereas in a left shift, a zero is appended to the lsb. the contents of the p register remain unchanged. in two multiply instructions, maa and maasu , the p register is also aligned. in other words, after the p register is sign-extended and shifted according to the ps ?eld, it is also shifted 16 bits to the right. 6. move instructions that use the accumulator (ax or bx) as a destination are sign extended. instructions that specify the accumulator-low (axl or bxl) as a destination clear the accumulator- high and the accumulator-extension. therefore, these instructions are sign-extension suppressed. all instructions using the accumulator-high (axh or bxh) as a destination clear the accumulator-low. these instructions are sign extended. an exception is: mov direct address, axh, [eu] . when the eu option is used, data is moved into accumulator-high without sign extension (the accumulator-extension axe is unaffected). 7. in all arithmetic operations between 16-bit registers and ax (36 bits), the 16-bit register is regarded as the 16 low-order bits of a 36-bit operand with a sign extension in the most-signi?cant bits. 8. the condition ?eld is almost always an optional ?eld, except when it is followed by another optional ?eld, as in the reti instruction. when the condition ?eld is the last ?eld of the instruction and the condition is omitted, the condition defaults to true. for example, shr4 true is the same as shr4 . in the instruction reti true, context , the true cannot be omitted. 9. arithmetic and logical operations (not bit manipulation operations) using the same accumulator as the source (soperand) and the destination (doperand) are not permitted. for example, add a0, a0 is not invalid but shfc a0, a0 is. 10. an instruction that immediately follows another which has modi?ed the rb register may not use the index addressing mode. the only exception is when rb is modi?ed using a long immediate operand ( mov ##long immediate, rb ).
7-10 instruction set 11. all commands that use pc as a destination register must be followed with two nop instructions. the only exception to this statement is the mov ##long immediate, pc instruction, where only one nop is required. 7.3 instruction functional groups this section contains an overview of all core instructions, and provides additional information on selected groups of instructions. table 7.7 contains a comprehensive list of all the CWDSP1650 instructions, grouped by function, and the page number where information about each instruction can be found. table 7.7 CWDSP1650 instruction set listing function operation description page arithmetic and logical instructions add add 7-18 sub subtract 7-180 or logical or 7-137 and logical and 7-28 xor logical exclusive or 7-200 cmp compare 7-48 addl add to low accumulator 7-23 subl subtract from low accumulator 7-185 addh add to high accumulator 7-21 subh subtract from high accumulator 7-183 cmpu compare unsigned 7-51 addv add long immediate value 1 7-25 subv subtract long immediate value 1 7-187 cmpv compare long immediate value 1 7-53 norm normalize 7-134 (sheet 1 of 5)
instruction functional groups 7-11 arithmetic and logical instructions (cont.) divs division step 7-61 max maximum between two ax-accumulators 7-86 maxd maximum between data memory location and ax- accumulator 7-88 min minimum between two ax-accumulators 7-90 lim limit ax-accumulator 7-67 moda modify ax-accumulator conditionally 7-92 moda modi?cations: 2 shr shift right 7-172 shr4 shift right four 7-174 shl shift left 7-168 shl4 shift left four 7-170 ror rotate right through carry 7-159 rol rotate left through carry 7-158 not logical not 7-136 neg twos compliment 7-132 clr clear 7-46 copy copy other accumulator 7-58 rnd round upper 20 bits 7-157 pac r product move and round 7-140 clrr clear and round 7-47 inc increment by one 7-66 dec decrement by one 7-59 multiply instructions mpy multiply 7-121 mpysu multiply signed by unsigned 7-127 mac multiply and accumulate previous product 7-76 table 7.7 CWDSP1650 instruction set listing (cont.) function operation description page (sheet 2 of 5)
7-12 instruction set multiply instructions (cont.) macsu multiply signed by unsigned and accumulate previous product 7-78 macus multiply unsigned by signed and accumulate previous product 7-81 macuu multiply unsigned by unsigned and accumulate previous product 7-83 maa multiply and accumulate aligned previous product 7-72 maasu multiply signed by unsigned and accumulate aligned previous product 7-74 msu multiply and subtract previous product 7-129 mpyi multiply signed short immediate 7-123 sqr square 7-176 sqra square and accumulate previous product 7-178 bmu instructions set set bit field 7-162 rst reset bit field 7-160 chng change bit field 7-44 tst0 test bit field for zeroes 7-193 tst1 test bit field for ones 7-195 tstb test speci?c bit 7-198 shfc shift accumulators according to shift value register conditionally 7-164 shfi shift accumulators by an immediate shift value 7-166 exp evaluate the exponent value 7-64 modb modify bx-accumulator conditionally 7-96 modb modi?cations: 2 shr shift right 7-172 shr4 shift right four 7-174 shl shift left 7-168 table 7.7 CWDSP1650 instruction set listing (cont.) function operation description page (sheet 3 of 5)
instruction functional groups 7-13 bmu instructions (cont.) modb modi?cations: (cont.) shl4 shift left four 7-170 ror rotate right through carry 7-159 rol rotate left through carry 7-158 clr clear 7-46 move instructions mov move data 7-101 movp move from program memory into data memory 7-113 movd move from data memory into program memory 7-112 movs move and shift according to shift value register 7-117 movsi move and shift according to an immediate shift value 7-119 movr move and round 7-115 push push register or long immediate value onto stack 7-143 pop pop from software stack into register 7-141 swap swap ax and bx accumulators 7-190 banke bank exchange 7-32 branch/call instructions br conditional branch 7-37 brr relative conditional branch 7-39 call conditional call subroutine 7-40 callr relative condition call subroutine 7-42 calla call subroutine at location speci?ed by ax accumulator 7-41 ret return conditionally 7-147 retd delayed return 7-149 reti return from interrupt conditionally 7-151 retid delayed return from interrupt 7-153 rets return with short immediate parameter 7-155 table 7.7 CWDSP1650 instruction set listing (cont.) function operation description page (sheet 4 of 5)
7-14 instruction set 7.3.1 shift operations all shift operations are performed in a single cycle. each of the four accumulators can be shifted according to a six-bit signed number, representing -32 to +31 shifts, embedded in the instruction opcode. a left shift is indicated by a positive number; a right shift by a negative number. the sv register content can be used to cause a conditional shift of between -36 and +36 bits. conditional shifting supports calculating the amount of shifts at run time, as in normalization operations (refer to section 2.4.2.4, normalization. ) the source and the destination accumulators do not have to be the same. if the accumulators are different, the source accumulator is unaffected. for more information, refer to the shfc and shfi instructions. the shift and rotate operations included in the moda and modb instructions are also performed conditionally. moda and modb include one-bit right and left arithmetic-shift and rotate, and four-bit right and left arithmetic-shift. refer to the moda and modb instructions for more information. control and miscellaneous instructions nop no operation 7-133 modr modify register n 7-99 eint enable interrupt 7-63 dint disable interrupt 7-60 trap software interrupt 7-192 load load speci?c field into registers - page, modx, stepx, ps 7-69 cntx context switching store or restore 7-55 loop instructions rep repeat next instruction 7-145 bkrep block repeat 7-34 break break from a block-repeat 7-38 1. to or from a register or a data memory location. 2. shaded cells are modi?cations of either moda or modb. table 7.7 CWDSP1650 instruction set listing (cont.) function operation description page (sheet 5 of 5)
instruction functional groups 7-15 the status mode bit (s) in the st2 register determines whether the shift is arithmetic or logical. figure 7.1 shows an arithmetic right shift of an accumulator. during an arithmetic right shift, the most-signi?cant bits are sign extended and the least signi?cant bit is loaded into the c ?ag. figure 7.1 arithmetic shift right figure 7.2 shows a logical right shift of an accumulator. during a logical right shift, the most-signi?cant bits are ?lled with zeros. figure 7.2 logical shift right arithmetic left shifts and logical left shifts are performed identically (see figure 7.3 ). the arithmetic left shifts and logical left shifts both ?ll the least-signi?cant bits with zeros. figure 7.3 arithmetic and logical shift left 7.3.2 move and shift operations the move and shift operations (movs and movsi) perform in a single cycle. the accumulators are loaded from one of the registers or from a data memory location, addressed in direct addressing mode, or in indirect addressing mode, according to the sv shift value. the shifting range is +36 to -36, (shift left is indicated by a positive number; shift right by a negative number). the accumulators can also be loaded by one of the daau registers (rn registers) and shifted according to a constant embedded in the instruction. the shifting range in this case is +15 to -16. the status mode bit (s) in the st2 register determines whether the shift is arithmetic or logical, as described in section 7.3.1, shift operations. for more information, see the movs and movsi instructions in section 7.4, instruction set list. ? c extension high low 0 ? ? c extension high low c ? ? 0 extension high low
7-16 instruction set 7.3.3 rounding operations the movr and moda instructions can round the contents of the accumulator either in a single cycle or in parallel with other operations. for more information, see the movr and moda instructions. 7.3.4 division step operations the alu supports a single-cycle division step. for more details, see the divs instruction. 7.3.5 logical operations the and, or, and xor logical operations operate on 36 bit wide data. 16-bit operands are zero extended when used with these logical operations. the source and destination ax accumulators of these instructions are always the same. for example, the instruction and (r1), a0 ands the contents of register r1 with the contents of the a0 accumulator and stores the result in the a0 accumulator. logical operations between the two ax accumulators are also possible, for example, the instruction and a0, a1 ands the contents of the a0 and a1 accumulators together. the results are stored in accumulator a1. for details, refer to the detailed descriptions of the and, or, and xor instructions in this chapter. other logical operations are set, rst, chng, tst0, tst1, and tstb. these operations are executed on one of the registers or on data memory contents. refer to section 2.4.2.5, bit-field operations. 7.3.6 max and min instructions the max and min instructions are single-cycle operations used to ?nd maximum and minimum values. the two ax accumulators are compared and if the non-speci?ed accumulator is found to be the larger (or smaller for the min instruction) then this value overwrites the value in the speci?ed accumulator. hence, the speci?ed accumulator holds the maximum/minimum value of the two accumulators after the operation. the r0 pointer can be used in the same instruction as a buffer pointer, for example. r0 can be postmodified according to the specified mode in the instruction. if a new maximal or minimal number is found, the r0 pointer is also latched into the minimum/maximum pointer latching (mixp) register.
instruction set list 7-17 the maximum operation can also be performed directly on a data memory location pointed to by the r0 register (maxd instruction). with this single-cycle instruction, the maximal value is saved in the de?ned ax accumulator and the r0 value is written into the mixp register. in ?nding the maximum value, the pointer of the ?rst element or the last element is latched, using greater than (>), or equal or greater than ( 3 ) conditions, respectively. in ?nding the minimum value, the pointer of the ?rst element or the last element is latched, using less than (<), or equal or less than ( ) conditions, respectively. refer to the max, maxd, and min instructions in this chapter. for more details on the r0 and mixp registers, refer to section 4.2, daau registers. 7.3.7 multiplication instructions the core supports single- and double-precision multiplications. the signed-by-signed operation is used to multiply or multiply-accumulate the signed portions of the numbers. the signed-by-unsigned operation is used to multiply or multiply-accumulate the signed portion of the number with the lower, unsigned portion of the double-precision number. additional support for double-precision operations is given by shifting the p register 16 bits to the right before accumulating it, during a multiply- accumulate instruction, or to shift the partial multiplication result. 7.4 instruction set list the instruction set descriptions are listed alphabetically. each instruction de?nition contains the instruction format, syntax, instruction description, operation, ?ags, cycles, and an example. see section 7.3, instruction functional groups, for a listing of all instructions, grouped by function, and speci?c instruction page numbers. most core instructions are executed in a single cycle. the instruction execution time is denoted by xc, where x is the number of cycles. instructions that have a long immediate, long direct, or long index operand as one of the operand options take an additional cycle to execute. instructions that break the pipeline may have a different execution time depending on whether their condition is met or not met (for example, the call instruction). the execution time is indicated for both conditions in the cycles section.
add 7-18 instruction set add add opcode syntax add operand, ai description the contents of ai and operand are added to form either a 16-bit or a 32-bit result. the result is stored in ai[35:0]. if an operand other than p or aj register is selected, the contents of operand are added to ai[15:0] to form a 16-bit addition. if p or aj register is selected for the operand, p[31:0] is added to ai[31:0]. in both cases, the sign is extended through ai[35:32]. 15 13 12 9 8 7 0 short direct 101 0011 i direct 15 13 12 9 8 7 3 2 0 long direct (msw) 110 1010 i 11111 011 15 0 long direct (lsw) long direct 15 1312 987 5432 0 indirect 100 0011 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 0011 i 101 reg 15 12 11 9 8 7 0 short immediate 1100 011 i short immediate 15 12 11 9 8 7 5 4 0 long immediate (msw) 1000 011 i 110 xxxxx 15 0 long immediate (lsw) long immediate
instruction set list 7-19 add chapter 7 instruction set instruction set list add add operation ai ? ai + operand operand = reg 1 (rn) short direct address [##direct address] #unsigned short immediate ##long immediate (rb + offset7) (rb+##offset) 1. the reg cannot be ai or bi. flags affected cycles 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 long direct 2 2 indirect 1 1 register 1 1 short immediate 1 1 long immediate 2 2 short index 1 1 long index 2 2
add 7-20 instruction set add add examples add (r0), a0 before execution: after execution: add 0x100, a0 before execution: after execution: add ##0x1001, a0 before execution: after execution: a0: 0 8000 0000 (r0): 001e a0: 0 8000 001e (r0): 001e a0: 0 0000 0000 0x100: 00ff a0: 0 0000 00ff 0x100: 00ff a0: 0 1234 ffe0 a0: 0 1235 0fe1
addh instruction set list 7-21 addh add to high accumulator opcode syntax addh operand, ai description the contents of operand are added to ai[31:16] to form a 16-bit addition. ai[15:0] is unaffected after the operation. operation ai + operand * 2 16 ? ai the ail is unaffected. operand = reg 1 (rn) short direct address 1. the reg cannot be bi, ai, or p. flags affected cycles 15 13 12 9 8 7 0 short direct 101 1001 i direct 15 1312 987 5432 0 indirect 100 1001 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1001 i 101 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1
addh 7-22 instruction set addh add to high accumulator examples addh b1h, a0 before execution: after execution: addh (r0)+, a0 before execution: after execution: a0: 0 10ee 8000 b1h: e320 a0: f f40e 8000 b1h: e320 a0: 0 10ee 8000 r0: 0006 0x0006: 0200 0x0007: 9476 a0: 0 10ee 8200 r0: 0007 0x0006: 0200 0x0007: 9476
addl instruction set list 7-23 addl add to low accumulator opcode syntax addl operand, ai description the contents of operand are added to ai[15:0] to form a 16-bit addition. sign-extension of operand is suppressed for this operation. operation ai + operand ? ai operand = reg 1 (rn) short direct address 1. the reg cannot be bi, ai, or p. flags cycles 15 13 12 9 8 7 0 short direct 101 1010 i direct 15 1312 987 5432 0 indirect 100 1010 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1010 i 101 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1
addl 7-24 instruction set addl add to low accumulator example addl lc, a0 before execution: after execution: a0: 0 4320 8000 lc: ffff a0: 0 4321 7fff lc: ffff
addv instruction set list 7-25 addv add long immediate value to a register or a data memory location opcode syntax addv ##long immediate, doperand description the contents of long immediate value are added to doperand to form a 16-bit result. the result of the operation is stored in the doperand. the operand and long immediate values are sign-extended before the addition. if the doperand is not part of an accumulator ( ail , aih , aie , bil ,or bih ) then the accumulators are unaffected. if the operand is part of an accumulator, only the addressed part is affected. operation doperand ? ##long immediate + doperand doperand = reg 1 (rn) short direct address 1. the reg cannot be bi, ai, p, or pc. note that ai can be used in add ##long immediate, ai instruction. 15 12 11 9 8 7 0 short direct 1110 011 1 direct 15 1211 98 5432 0 indirect 1000 011 0111 mod rn 15 12 11 9 8 5 4 0 register 1000 011 1111 reg
addv 7-26 instruction set addv add long immediate value to a register or a data memory location flags affected z, m, and c are a result of the 16-bit operation. bit 15 affects the m ?ag. when the operand is not st0: when adding a long immediate value to st0, the result is stored in st0. when adding a long immediate value to st1, the ?ags are affected by the alu output, as usual. note that when the operand is part of an accumulator ( ail , aih , aie , bil ,or bih ), only the addressed part is affected. for example, if the instruction addv ##long immediate , a0l generates a carry, the carry ?ag is set, however, a0h is unchanged. on the other hand, the instruction addl ##long immediate, a0l (with same a0 and immediate values) changes the a0h and affects the carry ?ag according to bit 36 of the alu result. when the operand is st0: st0 (including the ?ags) accepts the addition result, regardless of the a0e bits. cycles 15 1211109876543210 st0: a0e z mnv c e l r im1 im0 ie sat cycles words short direct 2 2 indirect 2 2 register 2 2
addv instruction set list 7-27 addv add long immediate value to a register or a data memory location examples addv ##0xfe00, a0l before execution: after execution: addv ##0x0002, 0 before execution: after execution: a0: 0 3000 3f01 a0: 0 3000 3d01 0x100: 0120 page: 01 0x100: 0122 page: 01
and 7-28 instruction set and and opcode 15 13 12 9 8 7 0 short direct 101 0001 i direct 15 13 12 9 8 7 3 2 0 long direct (msw) 110 1010 i 11111 001 15 0 long direct (lsw) long direct 15 13 12 9 8 7 5 4 3 2 0 indirect 100 0001 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 0001 i 101 reg 15 12 11 9 8 7 0 short immediate 1100 001 i short immediate 15 12 11 9 8 7 5 4 0 long immediate (msw) 1000 001 i 110 xxxxx 15 0 long immediate (lsw) long immediate 15 12 11 9 8 7 6 0 short index 0100 001 i 0 offset 15 12 11 9 8 7 6 3 2 0 long index (msw) 1101 010 i 0 11011 001 15 0 long index (lsw) long index
and instruction set list 7-29 and and syntax and operand, ai description the contents of operand are combined with the contents of ai in a bitwise logical-and operation. if p or aj is selected for operand, ai[35:0] is logically anded with operand and the result is stored in ai[35:0]. if the operand is short immediate, the operand is zero-extended to form a 36-bit operand, then anded with the destination accumulator. bits [15:8] are unaffected; other bits of the accumulator are cleared. the instruction and #unsigned short immediate, ai can be used for masking out (clearing) some of the low-order bits at a 16-bit destination. the example below shows masking out of the top 8 bits of a memory location: mov (r0), a0 and #0xf, a0 mov a0, (r0) using the and instruction, bits [15:8] are unaffected, therefore the high- order bits at the destination do not change. see also the rst instruction. if the operand is a 16-bit register or a long immediate value, the operand is zero-extended to form a 36-bit operand, then anded with the accumulator. therefore, this instruction clears the upper bits of the accumulator. operation if operand is ai or p ai[35:0] and operand ? ai[35:0] if operand is unsigned short immediate ai[7:0] and operand ? ai[7:0] ai[15:8] ? ai[15:8] 1 0 ? ai[35:16] if operand is reg, (rn), long immediate ai[15:0] and operand ? ai[15:0] 0 ? ai[35:16]
and 7-30 instruction set and and operand = reg 1 (rn) short direct address [##direct address] #unsigned short immediate ##long immediate (rb+offset7) (rb+##offset) 1. the reg cannot be bi. flags note: the z ?ag is set if all alu output bits after the operation are zero; otherwise, it is cleared. when the operand is unsigned short immediate, alu output bit [35:8] = 0 bits [7:0] = ai[7:0] and operand. cycles 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words short direct 1 1 long direct 2 2 indirect 1 1 register 1 1 short immediate 1 1 long immediate 2 2 short index 1 1 long index 2 2
and instruction set list 7-31 and and example and #30, a0 before execution: after execution: a0: 0 0820 ffff a0: 0 0000 ff1e
banke 7-32 instruction set banke bank exchange opcode syntax banke [r0] [,r1] [,r4] [,cfgi] description exchange the list of operands with their respective shadow registers. the bank bits select the registers to be exchanged, as shown below: assembler syntax examples: banke r0 banke r1, cfgi banke r1, r0 banke cfgi, r1, r4 for more details refer to section 6.3.6, context switching. operation operand ? operandb flags 15 76 43 0 banke 010010111 xxx bank bit number register 0r0 1r1 2r4 3 cfgi 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat
banke instruction set list 7-33 banke bank exchange flags affected this instruction does not affect the ?ags. cycles example banke r0 before execution: after execution: cycles words banke 1 1 r0: 2f01 r0b: 0100 r0: 0100 r0b: 2f01
bkrep 7-34 instruction set bkrep block repeat opcode syntax bkrep operand, addr description this instruction begins a block repeat that is to be repeated operand + 1 times. the value of operand can range from 0 to 65535. the start address of the code block to be repeated is the address after the bkrep instruction, and the last address is the one speci?ed by the addr ?eld. if the last instruction at the block repeat is a one-word instruction, addr is the address of this instruction. if the last instruction at the block repeat is a two-word instruction, add is the address of the second word of the instruction. the operand is inserted into the loop counter (lc) register. the inloop status bit lp is set to one indicating a block repeat loop. the block repeat nesting level counter is incremented by one. the repeated block is interruptible. this instruction can be nested. four levels of block repeat can be used. the block-repeat minimum length is two words. restrictions when using bkrep : 1. the break instruction cannot start at the last address of the block repeat loop. 2. the following instructions cannot start at addr C 1 of the block repeat loop: mov soperand, icr; mov icr, ab . 3. the following instructions cannot start at the last two addresses of the block repeat loop: instructions with lc or icr as a source, br, brr, call, callr, calla, ret, reti, rets, retd, retid, bkrep, and rep instructions with pc or lc as a destination. 15 87 54 0 register 01011101 xxx reg 15 8 7 0 # unsigned short immediate 01011100 short immediate
bkrep instruction set list 7-35 bkrep block repeat description (cont.) 4. the mov soperand, icr instruction and instructions with lc as a destination cannot start at addr C 2 of the block repeat loop. 5. the following instructions cannot start at the addr C 3 of the block repeat loop: set/rst/chng/addv/subv with lc as a destination. 6. notice that illegal instruction sequences are also restricted as the last and ?rst instructions of a block-repeat loop. 7. two block-repeats cannot have the same last address. operation operand ? lc 1 ? lp status bit bcx + 1 ? bcx operand: #unsigned short immediate 1 reg 2,3 1. when using an unsigned short immediate operand, the number of repetitions is between 1 to 256. when transferring the #unsigned short immediate number into the lc register, it is copied to the low-order eight bits of the lc. the high-order eight bits are cleared. 2. in the block-repeat outer level, the reg cannot be ai, bi, or p. in other block- repeat levels, the reg cannot be ai, bi, p, or lc. note: the assembler cannot check the restriction on the lc register in a nested block-repeat. 3. the data read while reading lc during a block repeat loop execution is of the loop counter. if the outer block repeat loop has ?nished normally the contents of lc is 0; if it was ?nished using break, the contents of lc will be the value of the loop counter at the breakpoint. flags affected this instruction does not affect the ?ags.
bkrep 7-36 instruction set bkrep block repeat cycles example bkrep #num1-1, >%main . . bkrep #num2-1, >%inner moda clr a0 . . %inner: mov a0h, (r0)+ . . %main: modr (r0)+ the outer loop that ends with label %main is executed num1 times while the inner loop that ends with label %inner is executed num2 times. these nested loops are executed without any overhead in wrapping around from the last statement of the loops to the ?rst statement of the loops. cycles words register 2 2 short immediate 2 2
br instruction set list 7-37 br conditional branch opcode syntax br address [, cond] description branch to the speci?ed address, if cond is met. if condition is met, address is the address/label of the new program memory location. the address is the second word of the instruction. operation if condition then address ? pc if condition is met, branch to the program memory location speci?ed by address . flags affected this instruction does not affect the ?ags. cycles example mov @var, a0 br process, eq the ?ags are set according to the contents of variable located at var by the mov @var, a0 instruction. if z = 1 in the st0 status register, the branch is executed. otherwise, the instruction following the branch instruction is executed. 15 6543 0 br 0100000110 xx cond cycles words br 2 (if no branch) 3 (if branch occurs) 2
break 7-38 instruction set break break from block repeat opcode syntax break description this instruction is used for breaking out of the current block-repeat loop. the internal registers which contain the ?rst address, last address and loop-counter are popped. the break instruction cannot be the last instruction of a block-repeat loop. a break at the outer level does not change lc and resets lp bit. operation none. flags affected this instruction does not affect the ?ags. cycles example bkrep #num, <%main . tsb @var, #15 brr <%continue, eq break brr %leaveloop . %continue: . . %main: . %leaveloop: bit 15 of the variable located at label var is tested. if the bit is not clear, the loop is terminated. if it is cleared, the loop continues. 15 6 5 0 break 1101001111 xxxxxx cycles words break 1 1
brr instruction set list 7-39 brr relative conditional branch opcode syntax brr offset [, cond] description if condition is met, a branch is executed to the program memory location: address of the brr instruction + offset + 1. the offset range is -63 to +64. (offset range is offset +1.) operation if condition then address of brr inst. + offset + 1 ? pc assembler syntax: brr offset [,cond] or brr $-offset [,cond] or brr label [,cond] when label is the new program memory location, the instruction word includes the relative address calculated by the assembler as follows: (label address) C ( brr address) C 1. flags affected this instruction does not affect the ?ags. cycles example this example tests bit 2 of the variable var . the branch instruction will cause a jump back to this test until the bit is cleared. %init: tstb @var, #2 brr <%init, eq 15 11 10 4 3 0 brr 01010 offset cond cycles words brr 2 1
call 7-40 instruction set call conditional call subroutine opcode syntax call address [,cond] description if condition is met, address is the address/label of the new program memory location. the address is the second word of the instruction. operation if condition then sp C 1 ? sp pc ? (sp) address ? pc if the condition is met, the stack pointer (sp) is predecremented, the program counter (pc) is pushed into the software stack, and a branch is performed to the program memory location speci?ed by address . flags affected this instruction does not affect the ?ags. cycles example the code segment ini of the routine subroutine is called within the main loop. bkrep #sample, >%main . call subroutine.ini . %main: 15 6543 0 call 0100000111 xx cond cycles words call 2 (if condition not met) 3 (if condition met) 2
calla instruction set list 7-41 calla call subroutine at location speci?ed by the ai accumulator opcode syntax calla ail description call subroutine indirect (address from ai1). the stack pointer (sp) is predecremented. the program counter (pc) is pushed onto the software stack, and a branch is executed to the address pointed to by accumulator-low. this instruction can be used to perform computed subroutine calls. operation sp C 1 ? sp pc ? sp ail ? pc flags affected this instruction does not affect the ?ags. cycles example in this example, the program address contained in a0l is called within the main loop. bkrep #sample, >%main . calla a0l . . %main: 15 9876543 0 calla 1101010 i 1 xx 0 xxxx cycles words calla 3 1
callr 7-42 instruction set callr relative conditional call subroutine opcode syntax callr offset [,cond] description if the condition is met, the stack pointer (sp) is predecremented, the program counter (pc) is pushed on to the software stack and a branch is executed to the program memory location (the callr instruction + offset + 1). the offset range is between -63 to +64, de?ned as offset +1. operation if condition then sp C 1 ? sp pc ? (sp address ? pc assembler syntax: callr $+offset [,cond] or callr $-offset [,cond] or callr label [,cond] new execution address is label. the instruction word includes the relative address calculated by the assembler as follows: (label address) C( callr address) C 1. flags this instruction does not affect the ?ags. 15 11 10 4 3 0 callr 00010 offset cond
callr instruction set list 7-43 callr relative conditional call subroutine cycles example in this example, code segment ini is called within the main loop if register r0 has not been decremented to zero (r ?ag clear). bkrep #sample, >%main . modr (r0)- callr >%ini, nr . %main: . . . %ini: . . ret cycles words callr 2 1
chng 7-44 instruction set chng change bit field opcode syntax chng ##long immediate, operand description change speci?c bit-?eld in a 16-bit operand according to a long immediate value. the long immediate value contains ones in the bit-?eld location. if the operand is not part of an accumulator ( ail , aih , aie , bil ,or bih ) then the accumulators are unaffected. if the operand is part of an accumulator, only the addressed part is affected. the operand and the long immediate values are sign-extension suppressed. operation operand xor ##long immediate ? operand operand = reg 1 (rn) short direct address 1. the reg cannot be ai, bi, or p. 15 12 11 9 8 7 0 short direct 1110 010 1 direct 15 1211 98 5432 0 indirect 1000 010 0111 mod rn 15 12 11 9 8 5 4 0 register 1000 010 1111 reg
chng instruction set list 7-45 chng change bit field flags affected when the operand is not st0 : when the operand is st0 : the speci?ed bits are changed according to the bit-?eld in the long immediate value, regardless whether or not the a0e bits have changed. when changing the a0e bits ( chng ##long immediate, st0 ) the ?ags are affected according to the long immediate value. when changing the a1e bits ( chng ##long immediate, st1 ), the ?ags are updated according to the alu output. cycles example chng ##0x7fff, a0l before execution: after execution: 15 1211109876543210 st0: a0e z mnvcelrim1im0iesat cycles words short direct 2 2 indirect 2 2 register 2 2 a0: 0 ffff 1011 a0: 0 ffff 6fee
clr 7-46 instruction set clr clear accumulator opcode syntax clr ai [, cond] or clr bi [, cond] description clear speci?ed accumulator to zero. also refer to the moda and modb instructions on pages 7-92 and 7-96 . operation clr ai: ai = 0 clr bi: bi = 0 flags affected cycles example clr a0, true before execution: after execution: 15 13 12 11 8 7 4 3 0 clr ai 011 i 0111 0110 cond 15 13 12 11 8 7 6 4 3 0 clr bi 011 i 0111 x 110 cond 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words clr 1 1 a1: 0 0013 3a05 a1: 0 0000 0000
clrr instruction set list 7-47 clrr clear and round a-accumulator opcode syntax clrr ai [, cond] description refer to the moda instruction on page 7-92 for complete descriptions of this instruction. operation ai = 0x8000 flags affected cycles example in this example, assume the m ?ag in st0 is set. clrr a1, lt before execution: after execution: 15 13 12 11 8 7 4 3 0 clrr 011 i 0111 1100 cond 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words clrr 1 1 a1: 0 0013 3a05 a1: 0 0000 8000
cmp 7-48 instruction set cmp compare opcode 15 13 12 9 8 7 0 short direct 101 0110 i direct 15 13 12 9 8 7 3 2 0 long direct (msw) 110 1010 i 11111 110 15 0 long direct (lsw) long direct 15 13 12 9 8 7 5 4 3 2 0 indirect 100 0110 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 0110 i 101 reg 15 12 11 9 8 7 0 short immediate 1100 110 i short immediate 15 12 11 9 8 7 5 4 0 long immediate (msw) 1000 110 i 110 xxxxx 15 0 long immediate (lsw) long immediate 15 12 11 9 8 7 6 0 short index 0100 110 i 0 offset 15 12 11 9 8 7 3 2 0 long index (msw) 1101 010 i 11011 110 15 0 long index (lsw) long index
cmp instruction set list 7-49 cmp compare syntax cmp operand, ai description the contents of ai are compared with the contents of operand and the appropriate ?ags are set accordingly. both ai and operand are treated as signed numbers. the operand is lsb adjusted and the comparison is made against ai. operation ai - operand operand = reg 1 (rn) short direct address [##direct address] #unsigned short immediate ##long immediate (rb + offset 7) (rb+##offset) 1. the reg cannot be bi. flags affected cycles 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 long direct 2 2 indirect 1 1 register 1 1 short immediate 1 1 long immediate 2 2 short index 1 1 long index 2 2
cmp 7-50 instruction set cmp compare example cmp #8, a0 before execution: after execution: z, m, n, v, c bits cleared, e bit set. a0: 0 0820 ffff a0: 0 0820 ffff
cmpu instruction set list 7-51 cmpu compare unsigned opcode syntax cmpu operand, ai description the contents of operand are compared with ai[15:0] with sign bits being ignored, and the ?ags are set accordingly. the sign extension of the operand is suppressed for this operation. operation ai - operand operand = reg 1 (rn) short direct address 1. the reg cannot be bi, ai, or p. in order to compare ai with an unsigned 16-bit operand, ai[35:16] should be cleared using either the mov ? ail instruction or other instructions). flags affected 15 13 12 9 8 7 0 short direct 101 1111 i direct 15 1312 987 5432 0 indirect 100 1111 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1111 i 101 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
cmpu 7-52 instruction set cmpu compare unsigned cycles example cmpu r4, a0 before execution: after execution: the z, n, v, e bits are cleared, m and c bits are set. cycles words short direct 1 1 indirect 1 1 register 1 1 a0: 0 0000 3a05 r4: 4000 a0: 0 0000 3a05 r4: 4000
cmpv instruction set list 7-53 cmpv compare long immediate value to a register or a data memory location opcode syntax cmpv ##long immediate, operand description the contents of long immediate value are compared with operand and the ?ags updated accordingly. the contents of the operand are unaffected after the operation. the operand and long immediate values are sign-extended prior to the comparison. operation operand - ##long immediate value operand = reg 1 (rn) short direct address 1. the reg cannot be bi, ai, p, or pc. note that ai can be used in the cmp ##long immediate, ai instruction. flags affected z, m, and c are the results of the 16-bit operation. m is affected by bit 15. note that the ?ags are set differently for the subv ##long immediate, st0 and cmpv ##long immediate, st0 instructions. 15 12 11 9 8 7 0 short direct 1110 110 1 direct 15 1211 98 5432 0 indirect 1000 110 0111 mod rn 15 12 11 9 8 5 4 0 register 1000 110 1111 reg 15 1211109876543210 st0: a0e z mnv c e l r im1 im0 ie sat
cmpv 7-54 instruction set cmpv compare long immediate value to a register or a data memory location cycles example cmpv ##0x004f, b0h before execution: after execution: the m and c bits are set, and the z bit cleared. cycles words short direct 2 2 indirect 2 2 register 2 2 b0: 0 0013 3a05 b0: 0 0013 3a05
cntx instruction set list 7-55 cntx context switching store or restore opcode syntax cntx s | r description this instruction activates the context switching mechanism. operation s - store the shadow/swap bits and swap a1 and b1 accumulators contents: the st0[0], st0[11:2], st1[11:10], and st2[7:0] bits are pushed to their shadow bits. the page bits st1[7 : 0] are swapped with their alternative register. a1 is transferred into b1 , b1 is transferred into a1 . r - restore the shadow/swap bits and swap a1 and b1 accumulators contents: the st0[0], st9[11:2], st1[11:10], and st2[7:0] bits are popped from their shadow bits. the page bits st1[7 : 0] are swapped with their alternative register. a1 is transferred into b1 , b1 is transferred into a1 . 15 6543 0 cntx (store) 1101001110 x 0 xxxx 15 6543 0 cntx (restore) 1101001110 x 1 xxxx
cntx 7-56 instruction set cntx context switching store or restore flags affected in a store, ?ags represent the data transferred into a1: in a restore, ?ags are restored from their shadow bits: cycles example cntx s before execution: 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words cntx 1 1 a1: 0 0000 0000 b1: 0 0007 00e0 st0: 0e20 st1: 0b00 st2: 1000
cntx instruction set list 7-57 cntx context switching store or restore example after execution: a1: 0 0007 00e0 b1: 0 0000 0000 st0: 0a20 st0s: 0e20 st1: 0b00 st1s: 0002 st2: 1000 st2s: 0000
copy 7-58 instruction set copy copy other a accumulator opcode syntax copy ai [, cond] description copy from contents of other a accumulator. also see the moda instruction on page 7-92 . operation ai = a i flags affected cycles example copy a0, eq (assume z bit is set before execution of the instruction) before execution: after execution: z, m, n, e are cleared. 15 13 12 11 8 7 4 3 0 copy 011 i 0111 1111 cond 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words copy 1 1 a0: 0 0780 0400 a1: 0 0007 00e0 a0: 0 0007 00e0 a1: 0 0007 00e0
dec instruction set list 7-59 dec decrement a accumulator by one opcode syntax dec ai [, cond] description decrement ai accumulator by one if cond is true. also see the moda instruction on page 7-92 . operation ai = ai - 1 [if cond=true] flags affected cycles example dec a, true before execution: after execution: z, n are set, m, v, c, e are cleared, l unaffected. 15 13 12 11 8 7 4 3 0 dec 011 i 0111 1110 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words copy 1 1 a0: 0 0000 0001 a0: 0 0000 0000
dint 7-60 instruction set dint disable interrupt opcode syntax dint description the ie bit is cleared, disabling interrupts. operation 0 ? ie flags affected this instruction has no affect on ?ags. cycles 15 6 5 0 dint 0100001111 xxxxxx cycles words dint 1 1
divs instruction set list 7-61 divs division step opcode syntax divs direct address, ai description this instruction performs a division step for division of ai by the contents of the direct address. the 16-bit dividend is stored in ail and the divisor is stored in the direct address. the aie and aih registers are overwritten during operation of the instruction. each divs operation calculates one quotient bit using a nonrestoring fractional division algorithm. to produce an n-bit quotient, the division instruction is executed n times, where n is the number of bits of precision desired in the quotient (0 n 16). after the execution of the operation, the quotient is stored in ail and the remainder is stored in aih. both the dividend and the divisor must be positive. operation ai - (direct address * 2 15 ) ? alu output if alu output < 0 then ai = ai * 2 else ai = alu output * 2 + 1 the 16-bit dividend is placed at accumulator low; the accumulator high and the accumulator extension are cleared. the divisor is placed at the direct address. for a 16-bit division, divs should be executed 16 times. after 16 times, the quotient is in the accumulator low and the remainder is in the accumulator high. the dividend and the divisor must both be positive. flags affected 15 987 0 divs 0000111 i direct 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat
divs 7-62 instruction set divs division step cycles example rep #15 divs 0x0050, a0 before execution: after execution: cycles words divs 1 1 a0: 0 0000 3c04 0050: 3420 a0: 0 07e4 0001 0050: 3420
eint instruction set list 7-63 eint enable interrupt opcode syntax eint description the ie bit is set, enabling interrupts. operation 1 ? ie flags affected this instruction has no affect on ?ags. cycles example after the parameters are initialized, an interrupt is enabled by setting ie. init: . mov ##ptr, r4 . eint 15 6 5 0 eint 0100001110 xxxxxx cycles words eint 1 1
exp 7-64 instruction set exp evaluate the exponent value opcode syntax exp soperand [, ai] description evaluate the exponent value of the operand. the operand can be either reg (one of the registers) or a data memory location. the exponent result, a signed six-bit value, is sign extended and written into the shift value register (sv) and optionally into one of the a-accumulators. the source operand (soperand) is unchanged. the instruction following an exp instruction cannot move from/to the sv register. the sv register is be used in shfc and movs instructions or as a temporary general purpose register. 15 98765432 0 indirect ai 1001100 i 01 x mod rn 15 987 54 0 register ai 1001000 i 010 reg 15 98765432 0 indirect sv 1001110 x 01 x mod rn 15 987 54 0 register sv 1001010 x 010 reg 15 987 54 10 bj, ai 1001000 i 011 xxxx j 15 987 54 10 bi, sv 1001010 x 011 xxxx i
exp instruction set list 7-65 exp evaluate the exponent value operation when using exp soperand : exponent (soperand) ? sv the soperand is unaffected. when using exp soperand, ai : exponent (soperand) ? sv and ai the soperand is unaffected. soperand: reg 1 (rn) 1. the reg cannot be p. flags this instruction does not affect the ?ags. cycles example exp(r0)+, a0 before execution: after execution: 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words indirect, ai 1 1 register, ai 1 1 indirect, sv 1 1 register, sv 1 1 a0: 0 8000 0000 (r0): 0020 a0: 0 0000 0009 (r0): 0020
inc 7-66 instruction set inc increment a accumulator by one opcode syntax inc ai [, cond] description increments speci?ed a accumulator. also see the moda instruction on page 7-92 . operation ai = ai + 1 [if cond=true] flags affected cycles example inc a, true before execution:: after execution:: z, n, m, v, c, e are cleared, l unaffected. 15 13 12 8 7 4 3 0 inc 011 i 0111 1101 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words copy 1 1 a0: 0 0000 0040 a0: 0 0000 0041
lim instruction set list 7-67 lim limit ai accumulator opcode syntax lim ai[,a i] description this instruction saturates ai accumulator with maximum positive or minimum negative value when the value in the accumulator exceeds maximum or minimum representable value. operation when using lim ai : if ai > 0x07fffffff then ai = 0x07fffffff else if ai < 0xf80000000 then ai = 0xf80000000 else ai is unaffected when using lim ai, a i: ai is unaffected if a i 3 0x07fffffff then ai = 0x07fffffff else if ai 0xf80000000 then a i = 0xf80000000 else a i = ai 15 6543 0 lim a0 0100100111 00 xxxx 15 6543 0 lim a0, a1 0100100111 01 xxxx 15 6543 0 lim a1, a0 0100100111 10 xxxx 15 6543 0 lim a1 0100100111 11 xxxx
lim 7-68 instruction set lim limit ai accumulator flags affected note: l ?ag is set when limitation occurs. cycles example lim a0 before execution: after execution: 15 1211109876543210 st0: a0e z m nvce l r im1 im0 ie sat 0 cycles words lim 1 1 a0: 0 8490 0000 a0: 0 7fff ffff
load instruction set list 7-69 load load speci?c fields into registers opcode syntax load #immediate, operand description load designated portion with immediate value. operation operand: #unsigned immediate 8 bit, page the page bits, the low-order 8 bits of st1, are loaded with an 8-bit constant (0 to 255). #unsigned immediate 9 bit, modi #unsigned immediate 9 bit, modj the modx bits, the high-order 9 bits of cfgi are loaded with a 9-bit constant (0 to 511 which means 1 to 512 modulo options). 15 8 7 0 load page 00000100 short immediate 15 12 11 10 9 8 0 load modi 0000 0 01 short immediate 15 12 11 10 9 8 0 load modj 0000 1 01 short immediate 15 11 10 9 7 6 0 load stepi 11011 0 111 short immediate 15 11 10 9 7 6 0 load stepj 11011 1 111 short immediate 15 76 210 load ps 010011011 xxxxx immed
load 7-70 instruction set load load speci?c fields into registers operation (cont.) #immediate 7 bit, stepi #immediate 7 bit, stepj the stepx bits, the low-order 7 bits of cfgi, are loaded with a 7-bit constant. #unsigned immediate 2-bit, ps the ps status bits, bits 10 and 11 of st1 are loaded with a two-bit constant. refer to figure 4.10 status register 1 (st1) for the encoding of the ps bits. the assembler syntax permits the use of lpg #unsigned short immediate , which is equivalent to load #unsigned short immediate, page . the page bits (the low-order eight bits of st1) are loaded with an eight-bit constant (0 to 255). flags affected this instruction does not affect the ?ags. cycles example load integer value 4 into stepi in cfgi register. load #4, stepi before execution: after execution: cycles words load 1 1 cfgi: 0020 cfgi: 0004
lpg instruction set list 7-71 lpg load the page bits opcode syntax lpg #unsigned short immediate description refer to the load instruction for a complete description of this instruction. 15 8 7 0 lpg 00000100 short immediate
maa 7-72 instruction set maa multiply and accumulate aligned previous product opcode syntax maa operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is aligned with sign- extension 16 bits to the right and is added to ai. the result is stored in ai. the signed operands are multiplied together and stored in p. operation ai + aligned & shifted p ? ai operand1 ? y 1 operand2 ? x signed y * signed x ? p operand1, operand2: y, short direct address y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in maa (rj), (ri), ai is between y-memory and x-memory only, where rj points to y-memory, ri points to x-memory. 15 12 11 10 9 8 7 0 y direct 1110 i 10 0 direct 15 121110 87 5432 0 y indirect 1000 i 100 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 100 010 reg 15 121110 87 5432 0 indirect long immediate (msw) 1000 i 100 000 mod rn 15 0 indirect long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 100 0 jj ii w qq
maa instruction set list 7-73 maa multiply and accumulate aligned previous product flags cycles example maa (r4)+, (r0)-, a1 before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2 (r4): ff20 (r0): 0200 a1: 0 4350 ffe3 p: 2345 6789 a1: 0 4351 2328 p: fffe 4000
maasu 7-74 instruction set maasu multiply signed by unsigned and accumulate aligned previous product opcode syntax maasu operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is aligned with sign- extension 16 bits to the right and is added to ai. the result is stored in ai. the signed operand1 is multiplied with the unsigned operand2, and the result is stored in p. operation ai + aligned & shifted p ? ai operand1 ? y 1 operand2 ? x signed y * unsigned x ? p operand1, operand2: y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in maasu (rj), (ri), ai is between x-memory and y-memory only, where rj points to y-memory, ri points to x-memory. 15 121110 87 5432 0 y indirect 1000 i 111 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 111 010 reg 15 121110 87 5432 0 indirect long immediate (msw) 1000 i 111 000 mod rn 15 0 indirect long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 111 0 jj ii w qq
maasu instruction set list 7-75 maasu multiply signed by unsigned and accumulate aligned previous product flags cycles example maasu (r4)+, (r0)-, a1 before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2 (r4): ff20 (r0): 0200 a1: 0 4350 ffe3 p: 2345 6789 a1: 0 4351 466d p: fffe 4000
mac 7-76 instruction set mac multiply and accumulate previous product opcode syntax mac operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as defined in the ps field in st1. the shifted value is added to ai. the result is stored in ai. the signed operands are multiplied together and stored in p. operation ai + shifted p ? ai operand1 ? y 1 operand2 ? x signed y * signed x ? p operand1, operand2: y, short direct address y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value 2. the reg cannot be ai, bi, or p. 3. the multiplication in mac (rj), (ri), ai is between y-memory and x-memory only, where rj points to y-memory, ri points to x-memory. 15 12 11 10 9 8 7 0 y direct 1110 i 01 0 direct 15 121110 87 5432 0 y indirect 1000 i 010 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 010 010 reg 15 121110 87 5432 0 long immediate (msw) 1000 i 010 000 mod rn 15 0 long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 010 0 jj ii w qq
mac instruction set list 7-77 mac multiply and accumulate previous product flags cycles example mac (r4)+, (r0)-, a1 before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2 (r4): 01ad (r0): 1980 a1: 0 4304 1768 p: 0000 8000 p: 002a bb80 a1: 0 42c8 0cb4
macsu 7-78 instruction set macsu multiply signed by unsigned and accumulate previous product opcode syntax macsu operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is added to ai. the result is stored in ai. the signed operand1 is multiplied with the unsigned operand2, and the result is stored in p. 15 12 11 10 9 8 7 0 y direct 1110 i 11 0 direct 15 121110 87 5432 0 y indirect 1000 i 110 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 110 010 reg 15 121110 87 5432 0 long immediate (msw) 1000 i 110 000 mod rn 15 0 long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 110 0 jj ii w qq
macsu instruction set list 7-79 macsu multiply signed by unsigned and accumulate previous product operation ai + shifted p ? ai operand1 ? y 1 operand2 ? x signed y * unsigned x ? p operand1, operand2: y, short direct address y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in macsu (rj), (ri), ai is between y-memory and x-memory only, where rj points to y-memory, ri points to x-memory. flags cycles 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2
macsu 7-80 instruction set macsu multiply signed by unsigned and accumulate previous product example macsu (r4)+, (r0)-, a1 before execution: after execution: (r4): ff26 (r0): 2341 a1: 0 4303 9768 p: 0000 4000 p: ffe1 faa6 a1: 0 4304 1768
macus instruction set list 7-81 macus multiply unsigned by signed and accumulate previous product opcode syntax macus operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is added to ai. the result is stored in ai. the unsigned operand1 is multiplied with the signed operand2, and the result is stored in p. operation ai + shifted p ? ai operand1 ? y 1 operand2 ? x unsigned y * signed x ? p operand1, operand2: y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in macus (rj), (ri), ai is between y-memory and x-memory only, where rj points to y-memory, ri points to x-memory. 15 121110 87 5432 0 y indirect 1000 i 011 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 011 010 reg 15 121110 87 5432 0 long immediate (msw) 1000 i 011 000 mod rn 15 0 long immediate (lsw) long immediate 15 121110 876543210 (rj),(ri) 1101 i 011 0 jj ii w qq
macus 7-82 instruction set macus multiply unsigned by signed and accumulate previous product flags cycles example macus (r4)+, (r1)-, a1 before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2 (r4): ff26 (r0): 2341 a1: 0 42c8 0cb4 p: 002a bb80 a1: 0 431d 83b4 p: 2322 faa6
macuu instruction set list 7-83 macuu multiply unsigned by unsigned and accumulate previous product opcode syntax macuu operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is added to ai. the result is stored in ai. the unsigned operands are multiplied together, and the result is stored in p. after using this instruction, the p register cannot be reconstructed. during an interrupt service routine that uses the p register, the p register should be saved before it is used and restored before returning from the interrupt. however, the p register cannot be reconstructed after a macuu instruction; it is, therefore, recommended that a dint instruction be put before the macuu instruction and an eint instruction be placed after the instruction which uses the result in the p register (the unsigned product). the instruction that uses the p register or the shifted p register as a source operand after a macuu instruction uses the unsigned result in p zero extended into 36 bits, and then shifted as de?ned in the ps ?eld. this behavior is in effect until a new signed product is generated or a new value is written to ph. 15 121110 87 5432 0 y indirect 1000 i 101 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 101 010 reg 15 121110 87 5432 0 long immediate (msw) 1000 i 101 000 mod rn 15 0 long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 101 0 jj ii w qq
macuu 7-84 instruction set macuu multiply unsigned by unsigned and accumulate previous product operation ai + shifted p ? ai operand1 ? y 1 operand2 ? x unsigned y * unsigned x ? p operand1, operand2: y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in macuu (rj), (ri), ai is between x-memory and y-memory only, where rj points to y-memory, ri points to x-memory. flags cycles 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2
macuu instruction set list 7-85 macuu multiply unsigned by unsigned and accumulate previous product example macuu (r4)+, (r0)-, a1 before execution: after execution: (r4): ff20 (r0): 0200 a1: 0 431d 83b4 p: 2322 faa6 a1: 0 8963 7900 p: 01fe 4000
max 7-86 instruction set max maximum of two ai accumulators opcode syntax max ai, (r0), ge | gt description this instruction is used to ?nd the maximal value of the two a accumulators. if a new maximal value is found, this value is saved in the de?ned accumulator (ai) and the r0 pointer value is saved in the mixp register. (note that the mixp cannot be read by the instruction following the max instruction). the r0 register is postmodi?ed as speci?ed in the instruction, regardless of the result of the comparison. operation when using ge: if a i 3 ai then ai = a i mixp = r0 r0 is postmodified when using gt: if a i > ai then ai = a i mixp = r0 r0 is postmodified flags affected 15 10987 5432 0 max (ge) 100001 0 i 011 mod xxx 15 10987 5432 0 max (gt) 100001 1 i 011 mod xxx 15 1211109876543210 st0: a0e z mnvcelrim1im0iesat
max instruction set list 7-87 max maximum of two ai accumulators cycles example max a0, (r0), ge before execution: after execution: (assuming m=0) cycles words max 1 1 a0: 0 0000 001b r0 ff00 a1: 0 040b 2b52 (r0): 0100 a0: 0 040b 2b52 mixp: ff00
maxd 7-88 instruction set maxd maximum of data memory location and ai accumulator opcode syntax maxd ai, (r0), ge | gt description this instruction is used for ?nding the maximal value of a data memory location pointed to by r0 and one of the a accumulators. in case r0 points to a larger or equal value than the accumulator, the new maximal value is transferred to the de?ned accumulator (ai) and the r0 pointer value is transferred into the mixp register. (note that the mixp cannot be read in the instruction following the maxd instruction). the r0 register is postmodi?ed as speci?ed in the instruction, regardless of whether the new maximal value is updated. operation when using ge: if (r0) 3 ai then ai = (r0) mixp = r0 r0 is postmodified when using gt: if (r0) > ai then ai = (r0) mixp = r0 r0 is postmodified flags note: m is set when the max value was found and the accumulator and mixp register were updated; cleared otherwise. 15 10987 5432 0 maxd (ge) 100000 0 i 011 mod xxx 15 10987 5432 0 maxd (gt) 100000 1 i 011 mod xxx 15 1211109876543210 st0: a0e z mnvcelrim1im0iesat
maxd instruction set list 7-89 maxd maximum of data memory location and ai accumulator cycles example this example searches for the maximum value in a data array pointed to by r0, stores the maximum value in a0, and stores its pointer in mixp. moda clr, a0 rep #7 maxd a0, (r0)+, ge nop mov mixp, r1 the array is as follows: before execution: after execution: cycles words maxd 1 1 array address contents ff00 0x0240 ff01 0x0053 ff02 0xaacc ff03 0x08c7 ff04 0x1ccc ff05 0x0020 ff06 0x0100 ff07 0x2540 a0: 0 0000 0000 r0: ff00 a0: 0 0000 2540 mixp: ff07
min 7-90 instruction set min minimum of two ai accumulators opcode syntax min ai, (r0), le | lt description this instruction is used to ?nd the minimal value of the two a accumulators. if a new minimal value is found the new value is saved in the de?ned accumulator ai and the r0 pointer value saved in the mixp register. the r0 register is postmodi?ed as speci?ed at the instruction, regardless of the result of the comparison of the accumulators. operation when using le: if a i ai then ai = a i mixp = r0 r0 is postmodified when using lt: if a i < ai then ai = a i mixp = r0 r0 is postmodified flags note: m is set when the min value was found and the accumulator and mixp register were updated; cleared otherwise. 15 1110987 5432 0 min (le) 10001 x 0 i 011 mod xxx 15 1110987 5432 0 min (lt) 10001 x 1 i 011 mod xxx 15 1211109876543210 st0: a0e z mnvcelrim1im0iesat
min instruction set list 7-91 min minimum of two ai accumulators cycles example min a0, (r0), lt before execution: after execution: (assuming m=1) in this example, a0 was the minimum value, so no changes occurred. cycles words min 1 1 a0: 0 0000 3907 a1: 0 5128 0338 a0: 0 0000 3907 a1: 0 5128 0338
moda 7-92 instruction set moda modify ai accumulator conditionally opcode func: 0000 shr 0001 shr4 0010 shl 0011 shl4 0100 ror 0101 rol 0110 clr 0111 reserved 1000 not 1001 neg 1010 rnd 1011 pacr 1100 clrr 1101 inc 1110 dec 1111 copy syntax moda func, ai [,cond] the assembler syntax permits omitting the moda ; for example, shr a0 is equivalent to moda shr, a0 . description the contents of ai are modi?ed according to func , and the ?ags are set accordingly. if cond is speci?ed, ai is modi?ed only when the condition is true and is unaffected when false. 15 13 12 8 7 4 3 0 moda 011 i 0111 func cond
moda instruction set list 7-93 moda modify ai accumulator conditionally operation func: shr ai = ai >> 1 shl ai = ai << 1 shr4 ai = ai >> 4 shl4 ai = ai << 4 ror rotate ai right through carry rol rotate ai left through carry clr ai = 0 copy ai = a i neg ai = -ai not ai = not (ai) rnd round upper 20 bits of the ai ai = ai+0x8000 pacr ai = shifted p 1 + 0x8000 clrr ai = 0x8000 inc ai = ai + 1 dec ai = ai - 1 1. shifted p register means that the p register is sign-extended to 36 bits and then shifted as de?ned in the ps ?eld, status register st1. flags affected arithmetic shift: shr, shl, shr4, and shl4 an arithmetic shift is performed when the s status bit in status register st2 is cleared. the c ?ag is set according to the last bit shifted out of the operand (shr = bit 0, shr4 = bit 3, shl = bit 35, shl4 = bit 32). for shl/shl4, the v ?ag is cleared if the operand being shifted could be represented in 35/31 bits for shl/shl4, respectively; set otherwise. for shr/shr4, the v ?ag is always cleared. 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
moda 7-94 instruction set moda modify ai accumulator conditionally flags affected (cont.) logical shift: a logical shift is performed when the s status bit in status register st2 is set. the c ?ag is set according to the last bit shifted out of the operand (shr = bit 0, shr4 = bit 3, shl = bit 35, shl4 = bit 32). ror c- set according to the lsb (bit 0) shifted out of the operand. rol c- set according to the msb (bit 35) shifted out of the operand. not, copy, clr, clrr neg, rnd, pacr inc, dec 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
moda instruction set list 7-95 moda modify ai accumulator conditionally cycles example in this example, assume the m ?ag in st0 is set. moda neg, a1, lt before execution: after execution: cycles words moda 1 1 a1: 0 0013 3a05 a1: 0 ffec c5fb
modb 7-96 instruction set modb modify bi accumulator conditionally opcode func: 000 shr 001 shr4 010 shl 011 shl4 100 ror 101 rol 110 clr 111 reserved syntax modb func, bi [,cond] or func bx [, cond] the assembler syntax permits omitting the modb ; e.g. shr b0 is equivalent to modb shr, b0 . description the contents of bi are modi?ed according to func , and the ?ags are set accordingly. if cond is speci?ed, bi is modified only when the condition is true and is unaffected when false. refer to section 7.1.2, number representation, and section 4.4, status registers, for more information. operation func: shr bi = bi >> 1 shl bi = bi << 1 shr4 bi = bi >> 4 shl4 bi = bi << 4 ror rotate bi right through carry rol rotate bi left through carry clr bi = 0 15 13 12 11 8 7 6 4 3 0 modb 011 i 1111 x func cond
modb instruction set list 7-97 modb modify bi accumulator conditionally flags arithmetic shift: shr, shl, shr4, and shl4 an arithmetic shift is performed when the s status bit in status register st2 is cleared. the c ?ag is set according to the last bit shifted out of the operand (shr = bit 0, shr4 = bit 3, shl = bit 35, shl4 = bit 32). for shl and shl4, the v ?ag is cleared if the operand being shifted could be represented in 35/31 bits for shl/shl4, respectively; v ?ag is set otherwise. the ?ags are always cleared with the shr and shrf instructions. logical shift: logical shift is performed when the s status bit in status register st2 is set. shr/shr4/shl/shl4 the c ?ag is set according to the last bit shifted out of the operand (shr = bit 0, shr4 = bit 3, shl = bit 35, shl4 = bit 32). rotate right: ror the c ?ag is set according to the lsb (bit 0) shifted out of the operand. 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat
modb 7-98 instruction set modb modify bi accumulator conditionally flags (cont.) rotate left: rol the c ?ag is set according to the msb (bit 35) shifted out of the operand clear: clr cycles example in this example, assume the m ?ag in st0 and the s ?ag in st2 are set (logical shift mode selected). modb neg, b1, lt before execution: after execution: 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words modb 1 1 b1: 0 4860 fe30 b1: 4 860f e300
modr instruction set list 7-99 modr modify rn opcode syntax modr (rn)[+|-|+s] [,dmod] description the contents of rn are modi?ed, and the ?ags are set accordingly. if dmod is speci?ed, rn is modi?ed based on the corresponding mn bit. operation when using modr (rn): rn is modified, influenced by the corresponding mn bit. when using modr (rn), dmod: rn is modified with modulo disabled. this instruction can also be used for loop control, the r bit providing an indication that the end of the loop has been reached: add: . modr (r0) - brr add, nr flags r ?ag is set if the 16-bit rn register is zero; otherwise it is cleared. cycles 15 765432 0 modr (modulo enabled) 000000001 x 0 mod rn 15 765432 0 modr (modulo disabled) 000000001 x 1 mod rn 15 1211109876543210 st0: a0e z m nvcel r im1 im0 ie sat cycles words modr 1 1
modr 7-100 instruction set modr modify rn example in this example, r3 is postincremented by one. modr (r3)+ before execution: after execution: r3: ff00 r3: ff01
mov instruction set list 7-101 mov move data opcode 15 10 9 5 4 0 register, register 010110 reg reg 15 1211109 65432 0 abl, dvm 1101 abl 1010 x 11 xxx 15 1211109 65432 0 abl, x 1101 abl 1011 x 11 xxx 15 1211109 765432 0 ab, ab 1101 ab 101 ab 10 xxx 15 654 0 register, mixp 0101111010 x reg 15 109 5432 0 register, indirect 000110 reg mod rn 15 5 4 0 mixp, register 01000111110 reg 15 9876543210 repc, ab 1101010 x 1 ab 10 x 00 15 654 0 register, icr 0100111111 x reg 15 987654 210 dvm, ab 1101010 x 1 ab 101 xx
mov 7-102 instruction set mov move data opcode (cont.) 15 9876543210 icr, ab 1101010 x 1 ab 10 x 10 15 9876543210 x, ab 1101010 x 1 ab 10 x 11 15 109 5432 0 indirect, register 000111 reg mod rn 15 5 4 0 (sp), register 01000111111 reg 15 12 11 9 8 7 0 indirect, direct 0010 rn* 0 direct 15 12 11 10 9 8 7 0 ail, direct 0011 1 i 0 0 direct 15 12 11 10 9 8 7 0 aih, direct 0011 1 i 1 0 direct 15 12 11 10 9 8 7 0 bil, direct 0011 0 i 0 0 direct 15 12 11 10 9 8 7 0 bih, direct 0011 0 i 1 0 direct 15 654 0 register, bi 010111011 i reg
mov instruction set list 7-103 mov move data opcode (cont.) 15 98765432 0 indirect, bi 1001100 i 11 x mod rn 15 8 7 0 sv, direct 01111101 direct 15 13 12 10 9 8 7 0 direct, indirect 011 rn* 00 direct 15 13 12 11 10 8 7 0 direct, ai 011 1 i 001 direct 15 13 12 11 10 8 7 0 direct, bi 011 0 i 001 direct 15 13 12 11 10 9 8 7 0 direct, bil 011 0 i 0 10 direct 15 13 12 11 10 9 8 7 0 direct, ail 011 1 i 0 10 direct 15 13 12 11 10 9 8 7 0 direct, bih 011 0 i 1 10 direct 15 13 12 11 10 9 8 7 0 direct, aih 011 1 i 1 10 direct 15 13 12 11 8 7 0 direct, aih [eu] 011 i 0101 direct 15 8 7 0 direct, sv 01101101 direct
mov 7-104 instruction set mov move data opcode (cont.) 15 987 54 0 long immediate, bi (msw) 0101111 i 001 xxxxx 15 0 long immediate, bi (lsw) long immediate 15 987 54 0 long immediate, register (msw) 0101111 x 000 reg 15 0 long immediate, register (lsw) long immediate 15 987 210 long direct, ai (msw) 1101010 i 101110 xx 15 0 long direct, ai (lsw) long direct 15 13 12 11 8 7 0 short immediate, ail 001 i 0001 short immediate 15 13 12 11 8 7 0 short immediate, aih 001 i 0101 short immediate 15 13 12 11 10 9 8 7 0 direct, bih 011 0 i 1 10 direct 15 13 12 11 10 9 8 7 0 direct, aih 011 1 i 1 10 direct 15 987 210 ail, long direct (msw) 1101010 i 101111 xx
mov instruction set list 7-105 mov move data opcode (cont.) 15 0 ail, long direct (lsw) long direct 15 9876 0 short index, ai 1101100 i 1 offset 15 987 210 long index, ai (msw) 1101010 i 100110 xx 15 0 long index, ai (lsw) long index 15 9876 0 ail, short index 1101110 i 1 offset 15 987 210 ail, long index (msw) 1101010 i 100111 xx 15 0 ail, long index (lsw) long index 15 13 12 10 9 8 7 0 short immediate, indirect 001 rn* 11 short immediate 15 13 12 10 9 8 7 0 short immediate, extx 001 ext 01 short immediate 15 8 7 0 short immediate, sv 00000101 short immediate 15 5 4 0 short immediate, icr 0100111110 short immediate
mov 7-106 instruction set mov move data syntax mov soperand, doperand description move the contents of the speci?ed source operand, soperand , to the speci?ed destination operand, doperand . operation soperand ? doperand soperand, doperand: reg, reg 1,2,3,4 reg, (rn) 1,2,5 (rn), reg 4,5 mixp, reg 4,6 reg, mixp 1,2,6 icr, ab x, ab dvm, ab repc, ab soperand, doperand: ail, x bil, x ail, dvm bil, dvm rn, direct address ail, direct address aih, direct address bil, direct address bih, direct address y, direct address rb, direct address sv, direct address direct address, rn direct address, ai direct address, ail direct address, aih [,eu] 10 direct address, bi direct address, bil direct address, bih direct address, y direct address, rb direct address, sv [##direct address], ai ail, [##direct address] (sp), reg 4,6 (rb+#offset7), ai
mov instruction set list 7-107 mov move data operation (cont.) (rb+##offset), ai ail, (rb+#offset7) ail, (rb+##offset) ##long immediate, reg 4 #unsigned short immediate, ail #signed short immediate, aih #signed short immediate, rn 9 #signed short immediate, y 9 #signed short immediate, rb 9 #signed short immediate, extx 9 #signed short immediate, sv 9 #signed immediate (5 bits), icr 7,8 1. the 32-bit p register can be transferred only to ai ( mov p, ai ). ph is a write- only register, therefore soperand cannot be ph. 2. a 36-bit accumulator can be a soperand only with a mov ab, ab instruction. 3. with mov reg, reg , the soperand cannot be the same as the doperand. 4. when the doperand reg is the pc register, two nop instructions must be placed after the mov soperand, pc instruction, except for the instruction mov ##long immediate, pc where only one nop should be inserted. 5. it is not permitted to move data from data address pointed by one of the indirect registers to the same indirect register (and vice versa) with post- modi?cation. 6. the reg cannot be bi. 7. enable or disable of context switching (by a write to icr ) takes effect after the next sequential instruction (e.g. when the user enables context switching for a speci?c interrupt, if the same interrupt is accepted immediately after the write to icr , it will not activate the context switching mechanism). 8. a mov soperand , icr cannot be followed by a bkrep instruction. 9. loading the doperand with a short immediate number causes sign-extension. 10. the eu ?eld is an optional ?eld. eu = accumulator extension is unaffected. refer to the following table. instruction fields accumulator fields contents after the instruction accumulator eu extension bits 16 msb aih/bih 16 lsb ail/bil ai/bi - sign-extended sign-extended data ail/bil - clear clear data aih/bih - sign-extended data clear aih eu unaffected data clear
mov 7-108 instruction set mov move data operation (cont.) conventions: the instruction at program memory address 0x0100: mov pc, ram after execution: (ram) = 0x0101. mov (r0), r0: before execution: after execution: flags when soperand is ail, aih, bil or bih: when doperand is ai or bi: if doperand is st0, st0 (including the ?ags) accepts the transferred data. there is no effect when doperand is not ac, bc, or st0, or when soperand is not ail , aih , bil ,or bih . r0: 0x20 ram address: 0x1000 r0: 0x1000 ram address: 0x1000 15 1211109876543210 st0: a0e z m nvce l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat
mov instruction set list 7-109 mov move data cycles cycles words register, register 1 1 register, (rn) 1 1 (rn), register 1 1 mixp, register 1 1 register, mixp 1 1 icr, ab 1 1 x, ab 1 1 ab, ab 1 1 dvm, ab 1 1 repc, ab 1 1 ail, x 1 1 bil, x 1 1 ail, dvm 1 1 bil, dvm 1 1 register, icr 1 1 rn*, direct 1 1 ail, direct 1 1 aih, direct 1 1 bil, direct 1 1 bih, direct 1 1 sv, direct 1 1 direct, rn* 1 1 direct, ai 1 1 direct, ail 1 1
mov 7-110 instruction set mov move data cycles (cont.) cycles words direct, aih 1 1 direct, bi 1 1 direct, bil 1 1 direct, bih 1 1 direct, aih, eu 1 1 direct, sv 1 1 long direct, ai 2 2 ail, long direct 2 2 (sp), register 1 1 short index, ai 1 1 long index, ai 2 2 ail, short index 1 1 ail, long index 2 2 long immediate, register 2 2 short immediate, ail 1 1 short immediate, aih 1 1 short immediate, rn* 1 1 short immediate, extx 1 1 short, sv 1 1 short immediate (5 bits), icr 1 1 register, bi 1 1 (rn), bi 1 1 long immediate, bi 2 2
mov instruction set list 7-111 mov move data example mov ##0x4560, a0 before execution: after execution: this operation affects the alu ?ags in the st0 status register. a0: 0 4500 6780 a0: 0 0000 4560
movd 7-112 instruction set movd move from data memory into program memory opcode syntax movd (ri), (rj) description move a word from data memory location pointed to by ri into program memory location pointed to by rj. operation ri - points to data memory location rj 1 - points to program memory location (ri) ? (rj) (ri) is postmodified (rj) is postmodified 1. the rj register cannot point to the movd instruction address or to ( movd address )+1. flags affected this instruction does not affect the ?ags. cycles example movd (r0)+, (r4)+ in this example, r0 points to a location in data memory, and r4 points to a location in program memory. both r0 and r4 are postincremented by one. before execution: after execution: 15 76543210 (ri), (rj) 010111111 jj ii w qq cycles words (ri), (rj) 4 1 (r4): 0000 (r0): 1234 (r4): 1234 (r0): 1234
movp instruction set list 7-113 movp move from program memory into data memory opcode syntax movp soperand, doperand description this instruction is used to move a word from program memory location pointed to by soperand into a data memory location pointed to by doperand or into reg. when using ai as soperand , the address is de?ned by ai-accumulator-low. operation soperand points to program memory location soperand ? doperand soperand, doperand: (ail), reg 1,2 (rn), (ri) 1. when the operand reg is the pc register, two nop instructions must be placed after the movp (ai), pc instruction. 2. the reg cannot be bi. flags affected when doperand is not an a accumulator or st0: this instruction does not affect the ?ags. when doperand is an a accumulator: when doperand is st0: 15 654 0 (ai), register 0000000001 i reg 15 98765432 0 (ri) 0000011 ii qq mod rn 15 1211109876543210 ac: a0e z m nvc e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
movp 7-114 instruction set movp move from program memory into data memory cycles example movp (r0)+, (r3)+ in this example, r0 points to a location in program memory, and r3 points to a location in data memory. both r0 and r3 are postincremented by one. before execution: after execution: cycles words (ai), register 3 1 (rn), (ri) 3 1 (r3): 0000 (r0): 1234 (r3): 1234 (r0): 1234
movr instruction set list 7-115 movr move and round opcode syntax movr operand, ai description the value stored in the operand is rounded and loaded into the ai . operation operand + 0x8000 ? ai operand: reg 1 (rn) 1. the reg cannot be bi. flags cycles 15 987 5432 0 indirect 1001110 i 111 mod rn 15 987 54 0 register 1001110 i 110 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words indirect 1 1 register 1 1
movr 7-116 instruction set movr move and round example movr (r0)+, a0 before execution: after execution: a0: 0 0000 3d03 (r0): 5678 a0: 0 0000 d678 (r0): 5678
movs instruction set list 7-117 movs move and shift according to shift value register opcode syntax movs operand, ab description the value stored in the operand is shifted by the amount stored in sv and loaded into ab. if the value in the sv is positive, the left shift is executed. if the value in the sv is negative, right shift is executed. if s ?ag in the st2 status register is set, the operation performs a logical shift. if cleared, it performs an arithmetic shift. operation if 0 < sv 36 then operand << sv ? ab if -36 sv < 0 then operand >> |sv| ? ab if sv = 0 then operand ? ab operand 2 : reg 1 (rn) direct address 1. the reg cannot be p. 2. when operand is ab, the assembler translates the instruction into a shfc : shfc a0, b0, true . 15 13 12 11 10 8 7 0 short direct 011 ab 011 direct 15 765432 0 indirect 000000011 ab mod rn 15 7654 0 register 000000010 ab reg
movs 7-118 instruction set movs move and shift according to shift value register flags arithmetic shift: if -36 sv 0 ( shift right), then the v ?ag is cleared. if 0 < sv < 36 (shift left) and the operand before being shifted can be represented in (36 Csv) bits then v is cleared. if sv = 36 (shift left) and the operand 1 0 then v is set. logical shift: note: if sv = 0, the c ?ag is cleared. cycles example this example assumes sv = 8. movs (r4), a0 before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1 a0: 0 0000 3f01 (r4): 001e a0: 0 0000 1e00 (r0): 001e
movsi instruction set list 7-119 movsi move and shift according to immediate shift value opcode syntax movsi operand, ab, #signed 5-bit immediate description the value stored in the operand is shifted by the immediate value and stored into the ab accumulator. if the immediate value is positive, a left shift is executed. if the immediate value is negative, a right shift is executed. if the s ?ag in the st2 status register is set, the operation is a logical shift. if s is cleared, an arithmetic shift is performed. operation the operand is sign-extended to 36 bits if 0 < #immediate 15 then operand << #immediate ? ab if -16 #immediate < 0 then operand >> #|immediate| ? ab if #immediate = 0 then operand ? ab operand: (rn) y rb flags arithmetic shift: 15 1211 987654 0 indirect 0100 rn* 01 ab immediate 15 1211 987654 0 y 15 1211 987654 0 rb 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
movsi 7-120 instruction set movsi move and shift according to immediate shift value flags (cont.) logical shift: note: if #immediate = 0 , the c ?ag is cleared. cycles example this example assumes that the s ?ag in st2 is cleared. movsi r4, a0, #8 before execution: after execution: 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat cycles words indirect, ab 1 1 a0: 0 0000 3e02 r4: ff00 a0: f ffff 0000 r4: ff00
mpy instruction set list 7-121 mpy multiply opcode syntax mpy operand1, operand2 description this instruction multiplies signed operand1 by signed operand2 and stores the result in p register. the operand1 is loaded into y input register with sign extension, and the operand2 is loaded into x multiplier input register with sign extension. 15 12 11 10 9 8 7 0 y direct 1110 i 00 0 direct 15 121110 87 5432 0 y indirect 1000 i 000 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 000 010 reg 15 121110 87 5432 0 indirect long immediate (msw) 1000 i 000 000 mod rn 15 0 indirect long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 000 0 jj ii w qq
mpy 7-122 instruction set mpy multiply operation operand1 ? y 1 operand2 ? x signed y * signed x ? p operand1, operand2: y, direct address y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in mpy (rj), (ri) is between x-memory and y-memory only, where rj points to y-memory, ri points to x-memory. flags this instruction does not affect the ?ags. cycles example mpy y, (r4)+ before execution: after execution: 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words short direct 1 1 indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2 y: 3709 (r4): 3240 p: 0acd 8440
mpyi instruction set list 7-123 mpyi multiply signed short immediate opcode syntax mpyi y, #signed short immediate description the immediate value is loaded into the x multiplier input register with sign extension. this instruction then multiplies the y input register with sign extension by the x multiplier input register. the result is stored in the product register. for pinedspcore compatibility the assembler syntax permits the use of mnemonic mpys y, #signed short immediate which is equivalent to mpyi y, #signed short immediate . operation #signed short immediate ? x signed y * signed x ? p flags this instruction does not affect the ?ags. cycles 15 8 7 0 short immediate 00001000 immediate 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words short immediate 1 1
mpyi 7-124 instruction set mpyi multiply signed short immediate example mpyi y, #0x20 before execution: after execution: y: 01ad p: 0000 35a0
mpys instruction set list 7-125 mpys multiply signed short immediate opcode syntax mpys y, #signed short immediate description the immediate value is loaded into the x multiplier input register with sign extension. this instruction then multiplies the y input register with sign extension by the x multiplier input register. the result is stored in the product register. for pinedspcore compatibility, the assembler syntax permits the use of mnemonic mpys y, #signed short immediate , which is equivalent to mpyi y, #signed short immediate . operation #signed short immediate ? x signed y * signed x ? p flags this instruction does not affect the ?ags. cycles 15 8 7 0 mpys 00001000 immediate 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words short immediate 1 1
mpys 7-126 instruction set mpys multiply signed short immediate example mpys y, #0x20 before execution: after execution: y: 01ad p: 0000 35a0
mpysu instruction set list 7-127 mpysu multiply signed by unsigned opcode syntax mpysu operand1, operand2 description this instruction multiplies signed operand1 by unsigned operand2 and stores the result in product register. the operand1 is loaded into y input register with sign extension, and the operand2 is loaded into x multiplier input register with sign extension. operation operand1 ? y 1 operand2 ? x signed y * unsigned x ? p operand1, operand2: y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, p. 3. the multiplication in mpysu (rj), (ri) is between x-memory and y-memory only, where rj points to y-memory, ri points to x-memory. 15 121110 87 5432 0 y indirect 1000 i 001 001 mod rn 15 12 11 10 8 7 5 4 0 y register 1000 i 001 010 reg 15 121110 87 5432 0 indirect long immediate (msw) 1000 i 001 000 mod rn 15 0 indirect long immediate (lsw) long immediate 15 121110 876543210 (rj), (ri) 1101 i 001 0 jj ii w qq
mpysu 7-128 instruction set mpysu multiply signed by unsigned flags this instruction does not affect the ?ags. cycles example mpysu y, (r4)+ before execution: after execution: 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words indirect 1 1 register 1 1 (rj), (ri) 1 1 long immediate 2 2 y: 3f01 (r4): 3240 p: 0c5d f240
msu instruction set list 7-129 msu multiply and subtract previous product opcode syntax msu operand1, operand2, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is subtracted from ai. the result is stored in ai. the signed operands are multiplied together and stored in p. 15 13 12 9 8 7 0 direct 101 1000 i direct 15 1312 987 5432 0 indirect 100 1000 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1000 i 101 reg 15 9876543210 (rj), (ri) 1101000 i 1 jj ii w qq 15 98765432 0 indirect long immediate (lsw) 1001000 i 11 x mod rn 15 0 indirect long immediate (msw) long immediate
msu 7-130 instruction set msu multiply and subtract previous product operation ai - shifted p ? ai operand1 ? y 1 operand2 ? x signed y * signed x ? p operand1, operand2: y, direct address y, (rn) y, reg 2 (rj), (ri) 3 (rn), ##long immediate 1. y ? y means that y retains its value. 2. the reg cannot be ai, bi, or p. 3. the multiplication in msu (rj), (ri), ai is between x-memory and y-memory only, where rj points to y-memory, ri points to x-memory. flags cycles 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words y, direct 1 1 y, indirect 1 1 y, register 1 1 (rj), (ri) 1 1 long immediate 2 2
msu instruction set list 7-131 msu multiply and subtract previous product example msu (r4)+, (r0)-, a1 before execution: after execution: (r0): 01ad (r4): 1980 a1: 0 0001 8000 p: 01fe 4000 a1: f fe03 4000 x: 01ad y: 1980 p: 002a bb80
neg 7-132 instruction set neg twos complement of a accumulator opcode syntax neg ai [, cond] description negate a accumulator. operation ai = -ai flags affected example neg a1 before execution: after execution: 15 13 12 8 7 4 3 0 neg 011 i 0111 1001 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat a1: 0 0013 3a05 a1: f ffec c5fb
instruction set list 7-133 nop chapter 7 instruction set instruction set list nop no operation opcode syntax nop description no operation occurs. operation nop no operation flags this instruction does not affect the ?ags. cycles 15 5 4 0 nop 00000000000 xxxxx 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words nop 1 1
norm 7-134 instruction set norm normalize opcode syntax norm ai, (rn) description this instruction normalizes a signed number in ai by evaluating the n ?ag in st1 each time norm is executed. if n = 0, rn is modi?ed as speci?ed to generate the magnitude of the exponent. it is assumed that rn and n are initialized before normalization begins. multiple executions of norm in conjunction with rep and brr may be required to completely normalize a value in ai. normalization can be also performed with exp and shift operations. the following code examples may be used to normalize a signed value in ai: option 1: rep #n norm a0, (r0)+ in this example the n ?ag is set when normalization is complete and no operation is performed for the remainder of the repeat loop. option 2: nrm: norm a0, (r0)+ brr nrm, nn in this example the norm instruction is only repeated while n is not set. normalization can also be performed (more ef?ciently) using the exp and shift instructions. for more details refer to section 2.4.2.4, normalization. 15 98765432 0 norm 1001010 i 11 x mod rn
norm instruction set list 7-135 norm normalize operation if n = 0 (ai is not normalized) ai = ai * 2 rn is modified as specified else nop nop this instruction is used to normalize the signed number at the accumulator. it affects the rn register. flags the r ?ag is updated in norm instruction only when rn pointer is modi?ed. the c ?ag is set according to the last bit shifted out of the operand (bit 35). cycles example rep #10 norm a0, (r0)+ before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words norm 2 1 a0: 0 0134 aec3 r0: 0000 a0: 0 4d2b b0c0 r0: 0006
not 7-136 instruction set not logical not opcode syntax not ai [, cond] description performs logical not on speci?ed a accumulator. also see the moda instruction on page 7-92 . operation ai = not(ai) flags affected example not a1 before execution: after execution: 15 13 12 8 7 4 3 0 not 011 i 0111 1000 cond 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat a1: 0 0013 3a05 a1: f ffec c5fa
or instruction set list 7-137 or logical or opcode 15 13 12 9 8 7 0 short direct 101 0000 i direct 15 12 11 9 8 7 3 2 0 long direct (msw) 1101 010 i 11111 000 15 0 long direct (lsw) long direct 15 1312 987 5432 0 indirect 100 0000 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 0000 i 101 reg 15 12 11 9 8 7 0 short immediate 1100 000 i short immediate 15 12 11 9 8 7 5 4 0 long immediate (msw) 1000 000 i 110 xxxxx 15 0 long immediate (lsw) long immediate 15 12 11 9 8 7 6 0 short index 0100 000 i 0 offset 15 12 11 9 8 7 3 2 0 long index (msw) 1101 010 i 11011 000 15 0 long index (lsw) long index
or 7-138 instruction set or logical or syntax or operand, ai description the contents of operand are combined with the contents of operand in a bitwise logical-or operation. if ai is selected as the operand, ai[35:0] is logically ored with operand and the result is stored in ai[35:0]. if p is selected as the operand, ai[31:0] is logically ored with operand and the result is stored in ai[31:0]. if operand is register or (rn), unsigned short immediate, long immediate then ai[15:0] ored with operand is stored in ai[15:0]. if the operand is one of the a-accumulators or the p register, it is ored with the destination accumulator. if the operand is a 16-bit register or an immediate value, the operand is zero-extended to form a 36-bit operand, then ored with the accumulator. therefore, this instruction does not affect the upper bits of the accumulator. operation or operand, ai if operand is ai ai[35:0] or ai[35:0] ? ai[35:0] if operand is p ai[31:0] or p[31:0] ? ai[31:0] if operand is reg, (rn), unsigned short immediate, long immediate ai[15:0] or operand ? ai[15:0] ai[35:16] ? ai[35:16] operand = reg 1 (rn) direct address [##direct address] #unsigned short ##long immediate (rb+offset7) (rb+##offset) 1. the reg cannot be bi.
or instruction set list 7-139 or logical or flags cycles example or (r2)+, a0 before execution: after execution: 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words short direct 1 1 long direct 2 2 indirect 1 1 register 1 1 long immediate 2 2 short immediate 1 1 index 1 1 long index 2 2 a0: 0 7520 0000 (r2): 0020 a0: 0 7520 0020 (r2): 0020
pac r 7-140 instruction set pacr product move and round to a accumulator opcode syntax pacr ai [, cond] description accumulator ai is loaded with the shifted value of the p register and rounded. if cond is speci?ed, ai is modi?ed only when the condition is true and is unaffected when it is false. operation pacr ai = shifted p 1 + 0x8000 1. shifted p register means that the p register is sign-extended to 36 bits and then shifted as de?ned in the ps ?eld, status register st1. flags affected 15 13 12 11 8 7 4 3 0 pacr 011 i 0111 1011 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
pop instruction set list 7-141 pop pop from stack into register opcode syntax pop reg description the top of stack is popped into one of the registers (reg) and the stack pointer, sp, is post-incremented. operation (sp) ? reg 1,2 sp + 1 ? sp 1. reg cannot be sp or bi. 2. a write into p is transferred into p-high (ph). flags if reg is not an a accumulator: if reg is an a accumulator: cycles 15 5 4 0 register 01011110011 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 ac: a0e z m nvc e l r im1 im0 ie sat cycles words register 1 1
pop 7-142 instruction set pop pop from stack into register example pop r3 before execution: after execution: sp: 0384 r3: 00fa 0x0384: 001b sp: 0385 r3: 001b
push instruction set list 7-143 push push register or long immediate value onto stack opcode syntax push operand description the stack pointer, sp, is predecremented, and the operand is pushed onto the software stack. the push instruction cannot follow mov soperand, sp (except for mov ##long immediate, sp); movp (ail), sp; addv/subv/set/rst/chng ##long immediate, sp . operation sp - 1 ? sp operand ? (sp) operand: reg 1 ##long immediate 1. the reg cannot be ai, bi, p, or sp. flags affected if operand is ail , aih , bil ,or bih , the l ?ag is affected; otherwise the ?ags are not affected. 15 5 4 0 register 01011110010 reg 15 6 5 0 long immediate (msw) 0101111101 xxxxxx 15 0 long immediate (lsw) long immediate 15 1211109876543210 a0e zmnvce l r im1 im0 ie sat
push 7-144 instruction set push push register or long immediate value onto stack cycles example push r3 before execution: after execution: cycles words register 1 1 long immediate 2 2 sp: 0384 r3: 00ff sp: 0383 0x383: 00ff
rep instruction set list 7-145 rep repeat next instruction opcode syntax rep operand description rep begins a single word instruction loop that is to be repeated operand + 1 times. repetition times are between 1C65536. the repeat mechanism is interruptible and the interrupt service routine can use another repeat (nested repeats). the nested repeat is uninterruptible. the following single word instructions cannot be repeated (most of these instructions break the pipeline): brr; callr; trap; ret; reti; retd; retid; rets; rep; calla; mov operand, pc; pop pc; movp (ai), pc; mov repc, ab . rep can be performed inside block-repeat ( bkrep ). operation operand: #unsigned short immediate 1 reg 2 1. when using an unsigned short immediate operand the number of repetitions is between 1 and 256. when transferring the #unsigned short immediate number into the repc register, it is copied to the low-order 8-bits of the repc. the high-order 8-bits are zero-extension of the low-order bits. 2. the reg cannot be ai, bi, or p. 15 87 54 0 register 00001101 xxx reg 15 8 7 0 short immediate 00001100 short immediate
rep 7-146 instruction set rep repeat next instruction flags affected this instruction does not affect the ?ags. cycles example rep #tap-1 mac (r4)+, (r1)-, a0 mac is executed #tap times. cycles words register 1 1 short immediate 1 1
ret instruction set list 7-147 ret return conditionally opcode syntax ret [cond] description this instruction is used to return from subroutines or interrupts. if the condition is met, the program counter (pc) is pulled from the software stack, while the previous program counter is lost, and the stack pointer (sp) is postincremented. this instruction can also be used as return from the maskable interrupt service routines (int0, int1, or int2). the ie bit in st0 must be set to one in order to re-enable interrupts if this is done. the trap/bi and nmi interrupt service routines must end with either a reti or a retid instruction. operation if condition then (sp) ? pc sp + 1 ? sp flags affected this instruction does not affect the ?ags (or ie bit). cycles 15 6543 0 ret 0100010110 xx cond cycles words ret 2 (return not performed) 3 (return performed) 1
ret 7-148 instruction set ret return conditionally example the main program calls the init section of the subroutine sub . after execution of ret , the program returns to the main routine and executes the next instruction ( mov a0h, @var ). main program: subroutine sub: main: .code sub mov @var, a0 init: .. .. call sub.init ret mov a0h, @var. .
retd instruction set list 7-149 retd delayed return opcode syntax retd description this instruction is used for a delayed return from subroutines or interrupts. two one-cycle instructions or one two-cycle instruction are/is fetched and executed, before executing the return. (the one-cycle instruction and the two-cycle instruction cannot be instructions that break the pipeline: brr; callr ; rep; trap; retd; retid; mov operand, pc; movp (ai), pc; pop pc . ) when the return occurs, the program counter (pc) is popped from the software stack (the previous program counter is lost) and the stack pointer (sp) is post-incremented. the retd instruction and the instruction(s) following the retd (two one- cycle instructions or one two-cycle instruction) are uninterruptible. this instruction can also be used as a return from the maskable interrupt service routines (int0, int1, or int2). to re-enable interrupts, the ie bit in st0 must be set. the trap/bi and nmi interrupt service routines must end with either a reti or a retid instruction. operation (sp) ? temporary storage sp + 1 ? sp two one-cycle instructions or one two-cycle instruction are/is executed temporary storage ? pc flags affected this instruction does not affect the ?ags. 15 6 5 0 retd 1101011110 xxxxxx
retd 7-150 instruction set retd delayed return cycles example the main program calls the init section of the subroutine sub . after executing add p, a1 , the program returns to the main routine and executes the next instruction ( mov a1h, @var ) after add p, a1 is executed. main program: subroutine sub: main: .code sub mov @var, a0 init: .. . retd call sub.init mac (r4)+, (r0)-, a1 mov a1h, @var add p, a1 cycles words retd 1 1
reti instruction set list 7-151 reti return from interrupt conditionally opcode syntax reti [cond [,context]] description this instruction is used to return from interrupt with or without interrupt context switching. if the condition is met, the program counter (pc) is pulled from the software stack, while the previous program counter is lost. the stack pointer (sp) is postincremented, and the ie bit in the st0 register is set to enable interrupts. ie is set only when returning from the int0, int1, or int2 service routine. the trap/bi and nmi interrupt service routines must end with either a reti or a retid instruction. operation if condition then (sp) ? pc sp + 1 ? sp 1 ? ie ;ie is set only when returning from into, ;int1, or int2 service routine. if context selected then same context restore operation is performed as for a cntx r instruction (see page 7-55 .) some assembler syntax examples are: reti reti ge reti true, context reti ge, context flags affected this instruction does not affect the ?ags. 15 6 5 4 3 0 reti (context switching disabled) 0100010111 x 0 cond 15 6 5 4 3 0 reti (context switching enabled) 0100010111 x 1 cond
reti 7-152 instruction set reti return from interrupt conditionally cycles example after the execution of reti , context is restored from the shadow registers, and the ie bit in the st0 status register is set. the context switching assumes that the ic0 bit in icr is set. int0: . . reti true, context cycles words reti 2 (return not performed) 3 (return performed) 1
retid instruction set list 7-153 retid delayed return from interrupt opcode syntax retid description delayed return from interrupt. the ie bit is set to enable interrupts, and the stack pointer (sp) is postincremented. ie is set only when returning from int0, int1, or int2 service routine. the two one-cycle instructions or one two-cycle instruction are/is fetched and executed before executing the return. the one-cycle instruction and the two-cycle instruction cannot be instructions that break the pipeline: brr; callr; rep; trap; retd; retid; move operand, pc; pop pc . when the return occurs, the program counter (pc) is popped from the software stack, and the previous program counter is lost. the retid instruction and the instruction(s) following the retid (two one- cycle instructions or one two-cycle instruction) are uninterruptible. operation (sp) ? temporary storage sp + 1 ? sp 1 ? ie ;ie is set only when returning from into, ;int1, or int2 service routine. two one-cycle instructions or one two-cycle instruction following retid instruction are/is executed temporary storage ? pc 15 6 5 4 3 0 retid 1101011111 x 0 xxxx
retid 7-154 instruction set retid delayed return from interrupt flags this instruction does not affect the ?ags. cycles example interrupted instruction is resumed after the execution of pop r2 . int0: . . retid pop r3 pop r2 15 1211109876543210 st0: a0e z m nvcelrim1im0iesat cycles words retid 1 1
rets instruction set list 7-155 rets return and adjust stack pointer with a short immediate offset opcode syntax rets #unsigned short immediate description this instruction is used to return from subroutines or interrupt service routines (for int0, int1, or int2) and to delete unnecessary parameters from the stack. the program counter (pc) is pulled from the software stack, while the previous program counter is lost. the stack pointer (sp) is post-incremented by one plus an eight-bit unsigned short immediate value. to enable more interrupts, you must set to one the ie bit in st0. operation (sp) ? pc sp + 1 + #immediate ? sp flags affected this instruction does not affect the ?ags. cycles 15 8 7 0 rets 00001001 short immediate cycles words rets 3 1
rets 7-156 instruction set rets return and adjust stack pointer with a short immediate offset example rets ##0x004f before execution: after execution: sp: 0x0020 0x0020: 0x0001 sp: 0x0070 pc: 0x0001
rnd instruction set list 7-157 rnd round upper 20 bits of a accumulator opcode syntax rnd ai [, cond] description round upper 20 bits of a accumulator if condition is met. also see moda instruction on page 7-92 . operation round upper 20 bits of ai ai = ai+0x8000 flags affected example rnd a1 before execution: after execution: 15 13 12 11 8 7 4 3 0 rnd 011 i 0111 1010 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat a1: 0 0013 3a05 a1: 0 0013 ba05
rol 7-158 instruction set rol rotate accumulator left through carry opcode syntax rol ai [, cond] or rol bi [, cond] description rotate speci?ed accumulator left if condition is met. the c ?ag bit is shifted into the lsb of the accumulator and then overwritten with bit 35 of that accumulator. also see moda instruction on page 7-92 and modb instruction on page 7-96 . operation if condition is true then ai/bi[35] = temporary storage ai/bi = (ai/bi << 1) + c c = temporary storage flags affected example rol a1 before execution: (assuming c ?ag cleared) after execution: c ?ag = 0 15 13 12 11 8 7 4 3 0 rol ai 011 i 0111 0101 cond 15 13 12 11 8 7 6 4 3 0 rol bi 011 i 0111 x 101 cond 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat a1: 0 1234 5678 a1: 0 2468 acf0
ror instruction set list 7-159 ror rotate accumulator right through carry opcode syntax ror ai [, cond] or ror bi [, cond] description rotate speci?ed accumulator right if condition is met. the c ?ag bit is shifted into the msb of the accumulator and then overwritten with bit 0 of that accumulator. also see moda instruction on page 7-92 and modb instruction on page 7-96 . operation if condition is true then ai/bi[0] = temporary storage ai/bi = (ai/bi >> 1) + c * 2 35 c = temporary storage flags affected example ror a1 before execution: (assuming c ?ag cleared) after execution: c ?ag = 0 15 13 12 11 8 7 4 3 0 ror ai 011 i 0111 0100 cond 15 13 12 11 8 7 6 4 3 0 ror bi 011 i 0111 x 100 cond 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat a1: 0 1234 5678 a1: 0 091a 2b3c
rst 7-160 instruction set rst reset bit field opcode syntax rst ##long immediate, operand description reset bit-?elds speci?ed in a 16-bit operand according to a long immediate value. the long immediate value contains ones in the bit-?eld locations to be reset. if the operand is not part of an accumulator ( ail , aih , aie , bil ,or bih ) then the accumulators are unaffected. if the operand is part of an accumulator, only the addressed part is affected. the operand and the long immediate values are sign-extension suppressed. operation operand and ##long immediate ? operand operand = reg 1 (rn) direct address 1. the reg cannot be ai, bi, p, or pc. 15 12 11 9 8 7 0 short direct 1110 001 1 direct 15 1211 98 5432 0 indirect 1000 001 0111 mod rn 15 12 11 9 8 5 4 0 register 1000 001 1111 reg
rst instruction set list 7-161 rst reset bit field flags when the operand is not st0: when the operand is st0: the speci?ed bits are reset according to the bit-?eld in the long immediate value, whether or not the a0e bits have changed. when resetting the a0e bits ( rst ##long immediate, st0 ) the ?ags are reset according to the long immediate value. when setting the a1e bits ( rst ##long immediate, st1 ), the ?ags are reset according to the alu output. cycles example rst ##0x004f, b0l before execution: after execution: 15 1211109876543210 st0: a0e z mnvcelrim1im0iesat cycles words short direct 2 2 indirect 2 2 register 2 2 b0: 0 0013 3a05 b0: 0 0013 3a00
set 7-162 instruction set set set bit field opcode syntax set ##long immediate, operand description set speci?c bit-?elds in a 16-bit operand according to a long immediate value, the long immediate value containing ones in the bit-?eld locations to be set. if the operand is not part of an accumulator ( ail , aih , bil ,or bih ) then the accumulators are unaffected. if the operand is part of an accumulator, only the addressed part is affected. the operand and the long immediate values are sign-extension suppressed. operation ##long immediate or operand ? operand operand = reg 1 (rn) direct address 1. the reg cannot be ai, bi, p, or pc. 15 12 11 9 8 7 0 short direct 1110 000 1 direct 15 1211 98 5432 0 indirect 1000 000 0111 mod rn 15 12 11 9 8 5 4 0 register 1000 000 1111 reg
set instruction set list 7-163 set set bit field flags when the operand is not st0: when the operand is st0: the speci?ed bits are set according to the bit-?eld in the long immediate value, regardless of whether or not the a0e bits have changed. when setting the a0e bits ( set ##long immediate, st0 ) ?ags are set according to the long immediate value. when setting the a1e bits ( set ##long immediate , st1 ), the ?ags are set according to the alu output. cycles example set ##7fff, a0l before execution: after execution: 15 1211109876543210 a0e z mnvcelrim1im0iesat cycles words short direct 2 2 indirect 2 2 register 2 2 a0: 0 0013 3a05 a0: 0 0013 7fff
shfc 7-164 instruction set shfc shift accumulators according to shift value register conditionally opcode syntax shfc soperand, doperand [, cond] description the contents of soperand are shifted according to the value in the sv register, and the result is stored into doperand if the condition is met. if a condition is not speci?ed, the operation is always executed. if the value in the sv register is positive, a left shift is executed. if the value in the sv register is negative, a right shift is executed. if the s ?ag in the st2 status register is set, a logical shift is executed. if s is zero, an arithmetic shift is executed. operation if condition is true then if 0 < sv 36 then soperand << sv ? doperand if -36 sv < 0 then soperand >> |sv| ? doperand if sv = 0 then soperand ? doperand 1 if soperand 1 doperand then soperand is unaffected soperand, doperand: ab, ab 1. in case the sv content is zero, this instruction is a conditional move between accumulators. 15 1211109 76543 0 shfc 1101 ab 101 ab 0 cond
shfc instruction set list 7-165 shfc shift accumulators according to shift value register conditionally flags arithmetic shift: if -36 sv 0 (shift right), then v is cleared. i f0 shfi 7-166 instruction set shfi shift accumulators by an immediate shift value opcode syntax shfi soperand, doperand, #signed 6-bit immediate description the contents of soperand are shifted according to the immediate value, and the result is stored in doperand . if the immediate value is positive, a left shift is executed; if negative, a right shift is executed. if the s ?ag in the st2 status register is set, a logical shift is executed. if zero, arithmetic shift is executed. operation if 0 < #immediate 31 then soperand << #immediate ? doperand if -32 #immediate < 0 then soperand >> #|immediate| ? doperand if #immediate = 0 then soperand ? doperand 1 if soperand 1 doperand then soperand is unaffected soperand, doperand: ab, ab 1. in case the immediate shift value is zero, this instruction can be used as a move instruction between the 36-bit accumulators. 15 12111098765 0 sh? 1001 ab 1 ab 1 immediate
shfi instruction set list 7-167 shfi shift accumulators by an immediate shift value flags arithmetic shift: if -32 #immediate 0 (shift right), then v is cleared. if 0 < #immediate 31 (shift left) and the operand before being shifted can be represented in 36 - immediate bits, then v is cleared. logical shift: note: if #immediate = 0, the c ?ag is cleared. cycles example shfi a0, a0, #-16 before execution: after execution: 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat cycles words sh? 1 1 a0: 0 8000 0000 a0: 0 0000 8000
shl 7-168 instruction set shl shift left opcode syntax shl ai [, cond] or shl bi [, cond] description shift speci?ed accumulator left if condition is met. also see moda instruction on page 7-92 and modb instruction on page 7-96 . if the s ?ag in the st2 status register is set, a logical shift is executed. if zero, arithmetic shift is executed. operation if condition is true then c = ai/bi[35] ai/bi = ai/bi <<1 flags affected arithmetic shift: the c ?ag is set according to bit 35. the v ?ag is cleared if the operand being shifted could be represented in 35 bits. logical shift: a logical shift is performed when the s status bit in status register st2 is set. the c ?ag is set according to bit 35 shifted out of the operand. 15 13 12 11 8 7 4 3 0 shl ai 011 i 0111 0010 cond 15 13 12 11 8 7 6 4 3 0 shl bi 011 i 0111 x 010 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat
shl instruction set list 7-169 shl shift left example shl a1 before execution: after execution: a1: 0 1987 6543 a1: 0 330e ca86
shl4 7-170 instruction set shl4 shift left by four opcode syntax shl4 ai [, cond] or shl4 bi [, cond] description shift speci?ed accumulator left by 4 if condition is met. also see moda instruction on page 7-92 and modb instruction on page 7-96 . if the s ?ag in the st2 status register is set, a logical shift is executed. if zero, arithmetic shift is executed. operation if condition is true then c = ai/bi[32] ai/bi = ai/bi << 4 flags affected arithmetic shift: the c ?ag is set according to bit 35. the v ?ag is cleared if the operand being shifted could be represented in 31 bits. logical shift: a logical shift is performed when the s status bit in status register st2 is set. the c ?ag is set according to bit 32 shifted out of the operand. 15 13 12 11 8 7 4 3 0 shl4 ai 011 i 0111 0011 cond 15 13 12 11 8 7 6 4 3 0 shl4 bi 011 i 0111 x 011 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat
shl4 instruction set list 7-171 shl4 shift left by four example shl4 a1 before execution: after execution: a1: 0 1987 6543 a1: 1 9876 5430
shr 7-172 instruction set shr shift right opcode syntax shr ai [, cond] or shr bi [, cond] description shift speci?ed accumulator right if condition is met. also see moda instruction on page 7-92 and modb instruction on page 7-96 . if the s ?ag in the st2 status register is set, a logical shift is executed. if zero, arithmetic shift is executed. operation if condition is true then c = ai/bi[0] ai/bi = ai/bi >> 1 flags affected arithmetic shift: the c ?ag is set according to bit 0. logical shift: a logical shift is performed when the s status bit in status register st2 is set. the c ?ag is set according to bit 0 shifted out of the operand. 15 13 12 11 8 7 4 3 0 shr ai 011 i 0111 0000 cond 15 13 12 11 8 7 6 4 3 0 shr bi 011 i 0111 x 000 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat
shr instruction set list 7-173 shr shift right example shr a1 before execution: after execution: a1: 0 1987 6543 a1: 0 0cc3 b2a1
shr4 7-174 instruction set shr4 shift right by four opcode syntax shr4 ai [, cond] or shr4 bi [, cond] description shift speci?ed accumulator right by 4 if condition is met. also see moda instruction on page 7-92 and modb instruction on page 7-96 . if the s ?ag in the st2 status register is set, a logical shift is executed. if zero, arithmetic shift is executed. operation if condition is true then c = ai/bi[3] ai/bi = ai/bi >> 4 flags affected arithmetic shift: the c ?ag is set according to bit 3. logical shift: a logical shift is performed when the s status bit in status register st2 is set. the c ?ag is set according to bit 3 shifted out of the operand. 15 13 12 11 8 7 4 3 0 shr4 ai 011 i 0111 0001 cond 15 13 12 11 8 7 6 4 3 0 shr4 bi 011 i 0111 x 001 cond 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat 15 1211109876543210 st0: a0e z m nv c e l r im1 im0 ie sat
shr4 instruction set list 7-175 shr4 shift right by four example shr4 a1 before execution: after execution: a1: 0 1987 6543 a1: 0 0198 7654
sqr 7-176 instruction set sqr square opcode syntax sqr operand description the operand is loaded into both the y input and x registers. both values are sign extended. the contents of the registers are multiplied together and stored in p. operation operand ? y operand ? x signed y * signed x ? p operand: (rn) reg 1 direct address 1. the reg cannot be ai, bi, or p. flags affected this instruction does not affect the ?ags. 15 13 12 9 8 7 0 short direct 101 1101 i direct 15 1312 987 5432 0 indirect 100 1101 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1101 i 101 reg
sqr instruction set list 7-177 sqr square cycles example sqr r1 before execution: after execution: cycles words short direct 1 1 indirect 1 1 register 1 1 r1: 1001 p: 0100 2001
sqra 7-178 instruction set sqra square and accumulate previous product opcode syntax sqra operand, ai description the previous product (p) is sign-extended to 36 bits and shifted as de?ned in the ps ?eld in st1. the shifted value is added to ai and the result is stored in ai. the operand is loaded into both the y and x inputs. both x and y are sign extended and are then multiplied together, the product is stored in the p register. operation ai + shifted p ? ai operand ? y operand ? x signed y * signed x ? p operand: (rn) reg 1 direct address 1. the reg cannot be ai, bi, or p. flags affected 15 13 12 9 8 7 0 short direct 101 1110 i direct 15 1312 987 5432 0 indirect 100 1110 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1110 i 101 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
sqra instruction set list 7-179 sqra square and accumulate previous product cycles example sqra (r1)+, a0 before execution: after execution: (assume ps bits in st1 are cleared) cycles words short direct 1 1 indirect 1 1 register 1 1 a0: 0 0000 007f (r1): 4000 p: 0000 1000 a0: 0 0000 107f p: 1000 0000
sub 7-180 instruction set sub subtract opcode 15 13 12 9 8 7 0 short direct 101 0111 i direct 15 1312 987 5432 0 indirect 100 0111 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 0111 i 101 reg 15 12 11 9 8 7 0 short immediate 1100 111 i short immediate 15 12 11 9 8 7 5 4 0 long immediate (msw) 1000 111 i 110 xxxxx 15 0 long immediate (lsw) long immediate 15 12 11 9 8 7 6 0 short index 0100 111 i 0 offset 15 12 11 9 8 7 3 2 0 long index (msw) 1101 010 i 11011 111 15 0 long index (lsw) long index 15 12 11 9 8 7 3 2 0 long direct (msw) 1101 010 i 11111 111 15 0 long direct (lsw) long direct
sub instruction set list 7-181 sub subtract syntax sub operand, ai description the contents of operand are subtracted from that of ai. the result is stored in ai[35:0]. if an operand other than p or aj register is selected, the contents of operand are subtracted from ai[15:0] to form a 16-bit subtraction. if the p or aj register is selected for the operand, aj/p[31:0] is subtracted from ai[31:0]. in both cases, the sign is extended through ai[35:32]. operation ai - operand ? ai operand = reg 1 (rn) direct address [##direct address] #unsigned short immediate ##long immediate (rb+offset7) (rb+##offset) 1. the reg cannot be bi. flags 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat
sub 7-182 instruction set sub subtract cycles example sub (r4), a0 before execution: after execution: cycles words short direct 1 1 long direct 2 2 indirect 1 1 register 1 1 short immediate 1 1 long immediate 2 2 index 1 1 long index 2 2 a0: 0 0820 1000 (r4): 0020 a0: 0 0820 0fe0
subh instruction set list 7-183 subh subtract from high accumulator opcode syntax subh operand, ai description the contents of operand are subtracted from ai[31:16] to form 16-bit result. ai[15:0] is unaffected after the operation. operation ai - operand * 2 16 ? ai operand = reg 1 (rn) direct address 1. the reg cannot be bi, ai, or p. flags affected cycles 15 13 12 9 8 7 0 short direct 101 1011 i direct 15 1312 987 5432 0 indirect 100 1011 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1011 i 101 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words short direct 1 1 indirect 1 1 register 1 1
subh 7-184 instruction set subh subtract from high accumulator example subh rb, a0 before execution: after execution: a0: 0 2045 4000 rb: 3450 a0: f ebf5 4000 rb: 3450
subl instruction set list 7-185 subl subtract from low accumulator opcode syntax subl operand, ai description the contents of operand are subtracted from ai[15:0] to form 16-bit result. sign-extension of operand is suppressed for this operation. operation ai - operand ? ai the operand is sign-extension suppressed. operand = reg 1 (rn) direct address 1. the reg cannot be bi, ai, or p. flags cycles 15 13 12 9 8 7 0 short direct 101 1100 i direct 15 1312 987 5432 0 indirect 100 1100 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 1100 i 101 reg 15 1211109876543210 st0: a0e z m n v c e l r im1 im0 ie sat cycles words direct 1 1 indirect 1 1 register 1 1
subl 7-186 instruction set subl subtract from low accumulator example subl r1, a0 before execution: after execution: a0: 0 2020 0000 r1: ff00 a0: 0 201f 0100 r1: ff00
subv instruction set list 7-187 subv subtract long immediate value from a register or a data memory location opcode syntax subv ##long immediate, operand description the contents of long immediate value are subtracted from operand to form a 16-bit result. the result of the operation is stored in operand. the operand and long immediate values are sign-extended. if the operand is not part of an accumulator ( ail , aih , aie , bil , and bih ) then the accumulators are unaffected. if the operand is part of an accumulator, only the addressed part is affected. operation operand - ##long immediate ? operand operand = reg 1 (rn) direct address 1. the reg cannot be bi, ai, or p. note that ai can be used in sub ##long immediate, ai instructions. 15 12 11 9 8 7 0 short direct 1110 111 1 direct 15 1211 98 5432 0 indirect 1000 111 0111 mod rn 15 12 11 9 8 5 4 0 register 1000 111 1111 reg 15 0 long immediate (lsw) long immediate
subv 7-188 instruction set subv subtract long immediate value from a register or a data memory location flags z, m, and c are the results of the 16-bit operation. m is affected by bit 15. when the operand is st0: st0 (including the ?ags) accepts the subtraction result, regardless of a0e bits. when the operand is not st0: when subtracting a long immediate value from st1, the alu output affects the ?ags. when the operand is part of an accumulator, only the addressed part is affected. for example, if the instruction subv ##long immediate, a0l generates a borrow and the carry ?ag is set, but a0h is unchanged. however, the instruction subl ##long immediate, a0l (with same a0 and immediate values) changes the a0h and affects the carry ?ag according to the 36-bit alu result. note: when using subv ##long immediate, st0 and cmpv ##long immediate, st0 , the ?ags are set differently. cycles 15 1211109876543210 a0e z mnv c e l r im1 im0 ie sat cycles words short direct 2 2 indirect 2 2 register 2 2
subv instruction set list 7-189 subv subtract long immediate value from a register or a data memory location example subv ##0x004f, b0h before execution: after execution: b0: 0 0013 3a05 b0: 0 ffc4 3a05
swap 7-190 instruction set swap swap accumulators opcode swap = 0000 a0 ? b0 0001 a0 ? b1 0010 a1 ? b0 0011 a1 ? b1 0100 a0 ? b0 and a1 ? b1 0101 a0 ? b1 and a1 ? b0 0110 a0 ? b0 ? a1 0111 a0 ? b1 ? a1 1000 a1 ? b0 ? a0 1001 a1 ? b1 ? a0 1010 b0 ? a0 ? b1 1011 b0 ? a1 ? b1 1100 b1 ? a0 ? b0 1101 b1 ? a1 ? b0 syntax refer to the operation section for the different swap mnemonics. description contents of selected ai and bi accumulators are exchanged. when the operation is x ? y ? z, then y ? z and x ? y. operation assembler mnemonics operation swap (a0, b0), (a1, b1) a0 ? b0 and a1 ? b1 swap (a0, b1), (a1, b0) a0 ? b1 and a1 ? b0 swap (a0, b0) a0 ? b0 swap (a0, b1) a0 ? b1 swap (a1, b0) a1 ? b0 swap (a1, b1) a1 ? b1 swap (a0, b0, a1) a0 ? b0 ? a1 swap (a0, b1, a1) a0 ? b1 ? a1 swap (a1, b0, a0) a1 ? b0 ? a0 swap (a1, b1, a0) a1 ? b1 ? a0 swap (b0, a0, b1) b0 ? a0 ? b1 swap (b0, a1, b1) b0 ? a1 ? b1 swap (b1, a0, b0 b1 ? a0 ? b0 swap (b1, a0, b0) b1 ? a0 ? b0 swap (b1, a1, b0) b1 ? a1 ? b0 15 6 5 4 0 swap 0100100110 xx swap
swap instruction set list 7-191 swap swap accumulators flags affected in the case of: swap (a0, b0), (a1, b1) swap (a0, b1), (a1, b0) the ?ags represent the data transferred into a0 . in all other cases: the ?ags represent the data transferred into ai. cycles example swap (a0, b0), (a1, b1) before execution: after execution: 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat cycles words swap 1 1 a0: 0 0000 1091 b0: 0 0346 5490 a1: 0 0000 8000 b1: 0 0fff 2300 a0: 0 0346 5490 b0 0 0000 1091 a1: 0 0fff 2300 b1: 0 0000 8000
trap 7-192 instruction set trap software interrupt opcode syntax trap description the stack pointer (sp) is predecremented. the program counter (pc), which points to the next instruction, is pushed onto the stack and into the dvm register. a branch to address location 0x0002 is executed. the interrupts (int0, int1, int2, nmi, or bi) are disabled regardless of the interrupt mask bits: ie, im0, im1, and im2 in st0 and im2 in st2. the trap instruction cannot be used in the trap/bi service routine. to return from the trap/bi service routine, use either the reti or retid instruction. the software interrupt (trap) and the breakpoint interrupt (bi) shares the same interrupt vector address. for more details on trap/bi, refer to section 6.3.3, trap/bi interrupts. note that both cdi and scanice based debug methods use the trap/bi interrupt. this precludes the use of the trap instruction when using the CWDSP1650 debugger. operation sp C 1 ? sp pc ? (sp) pc ? dvm 0x0002 ? pc disable interrupts (int0, int1, int2, nmi, bi) flags affected this instruction does not affect the ?ags. cycles 15 5 4 0 trap 00000000001 xxxxx cycles words tr a p 2 1
tst0 instruction set list 7-193 tst0 test bit field for zeros opcode syntax tst0 mask, operand description test whether a speci?ed bit-?eld of reg (one of the registers) or a data space location (using a direct or indirect addressing mode) is all zeros. the ?eld to be tested is speci?ed by a mask containing ones in the bit ?eld location. the mask is the content of an ax accumulator (ail) or a long immediate operand. the test operation affects the zero ?agthe ?ag is set if the speci?ed bit-?eld is all zeros, cleared otherwise. operation if (operand and mask) = 0x0000 then z = 1 else z = 0 mask = ail ##long immediate operand = reg 1 (rn) direct address 1. the reg cannot be ai, bi, or p. the instructions tst0 a0l, a0l ; tst0 a1l, a1l are illegal. the operand and the mask are sign-extension suppressed. 15 13 12 9 8 7 0 direct ai 101 0100 i direct 15 1312 987 5432 0 indirect ai 100 0100 i 100 mod rn 15 13 12 9 8 7 5 4 0 register ai 100 0100 i 101 reg 15 12 11 9 8 7 0 direct mask 1110 100 1 direct
tst0 7-194 instruction set tst0 test bit field for zeros flags cycles example tst0 ##0x004f, r1 before execution: after execution: z is set in the st0 status register. 15 1211109876543210 st0: a0e zmnvcelrim1im0iesat cycles words short direct 1 1 indirect 1 1 register 1 1 long immediate 2 2 r1: 0000 r1: 0000
tst1 instruction set list 7-195 tst1 test bit field for ones opcode syntax tst1 mask, operand description test whether all bits in the operand, speci?ed by the bit-?eld in mask, are set. the mask contains ones in the bit ?eld locations to be tested. the test operation affects the zero ?ag which is set if the speci?ed bit-?eld is all ones, cleared otherwise. 15 13 12 9 8 7 0 direct ai 101 0101 i direct 15 1312 987 5432 0 indirect ai 100 0101 i 100 mod rn 15 13 12 9 8 7 5 4 0 register ai 100 0101 i 101 reg 15 12 11 9 8 7 0 direct mask 1110 101 i direct 15 0 long immediate (lsw) long immediate
tst1 7-196 instruction set tst1 test bit field for ones operation if ( operand and mask) = 0x0000 then z = 1 else z = 0 mask = ail ##long immediate operand = reg 1 (rn) direct address 1. the reg cannot be ai, bi, or p. the instructions tst1 a0l, a0l ; tstl a1l, a1l are illegal. the operand and the mask are sign-extension suppressed. flags cycles 15 1211109876543210 st0: a0e zmnvcelrim1im0iesat cycles words short direct 1 1 indirect 1 1 register 1 1 long immediate 2 2
tst1 instruction set list 7-197 tst1 test bit field for ones example tst1 ##0x004f, r1 before execution: after execution: z is set in the st0 status register. r1: ffff r1: ffff
tstb 7-198 instruction set tstb test speci?c bit opcode syntax tstb operand, #bit number description test whether a speci?ed bit from operand is a one or a zero. the bit to be tested is speci?ed by the bit number (0-15). the test operation affects the zero ?agthe ?ag is set if the speci?ed bit is a one, cleared otherwise. operation if operand [bit number] = 1 then z = 1 if operand [bit number] = 0 then z = 0 operand = reg 1 (rn) direct address 0 bit number 15 1. the reg cannot be ai, bi, or p. flags the z ?ag re?ects the status of the tested bit. 15 12 11 8 7 0 direct 1111 bbbb direct 15 1211 87 5432 0 indirect 1001 bbbb 001 mod rn 15 12 11 8 7 5 4 0 register 1001 bbbb 000 reg 15 1211109876543210 st0: a0e zmnvcelrim1im0iesat
tstb instruction set list 7-199 tstb test speci?c bit cycles example tstb a0l, #7 before execution: after execution: z is set in the st0 status register. cycles words short direct 1 1 indirect 1 1 register 1 1 a0: 0 1010 008f a0: 0 1010 008f
xor 7-200 instruction set xor exclusive or opcode 15 13 12 9 8 7 0 short direct 101 0010 i direct 15 13 12 9 8 7 5 4 3 2 0 indirect 100 0010 i 100 mod rn 15 13 12 9 8 7 5 4 0 register 100 0010 i 101 reg 15 12 11 9 8 7 0 short immediate 1100 010 i short immediate 15 12 11 9 8 7 5 4 0 long immediate (msw) 1000 010 i 110 xxxxx 15 0 long immediate (lsw) long immediate 15 12 11 9 8 7 3 2 0 long direct (msw) 1101 010 i 11111 010 15 0 long direct (lsw) long direct 15 12 11 9 8 7 6 0 index 0100 010 i 0 offset 15 12 11 9 8 7 3 2 0 long index (msw) 1101 010 i 11011 010 15 0 long index (lsw) long index
xor instruction set list 7-201 xor exclusive or syntax xor operand, ai description the operand and ai are logically-xored and the result stored in ai .if p or ai is selected for operand, ai[35:0] is logically xored with operand and the result is stored in ai[35:0]. if the operand is a 16-bit register or an immediate value, the operand is zero-extended to form a 36-bit operand, then xored with the accumulator. therefore, this instruction does not affect the upper bits of the accumulator. operation ai ? ai xor operand operand = reg 1 (rn) direct address long direct address #unsigned short ##long immediate (rb+offset7) (rb+##offset) 1. reg cannot be bi. flags 15 1211109876543210 st0: a0e z m nvc e l r im1 im0 ie sat
xor 7-202 instruction set xor exclusive or cycles example xor ##0xffff, a0 before execution: after execution: cycles words short direct 1 1 long direct 2 2 indirect 1 1 register 1 1 short immediate 1 1 long immediate 2 2 index 1 1 long index 2 2 a0: 0 4320 e3dd a0: 0 4320 1c22
instruction opcode bit coding 7-203 chapter 7 instruction set 7.5 instruction opcode bit coding this section lists the opcodes with their respective bit encodings in tabular form. table 7.8 through table 7.24 list opcodes for the instructions in section 7.4, instruction set list. table 7.8 opcode i i (ai) description 0 accumulator a0 1 accumulator a1 table 7.9 opcode i or j i/j (bi) description 0 accumulator b0 1 accumulator b1 table 7.10 opcode ab ab/ab description 00 b0 01 b1 10 a0 11 a1
7-204 instruction set table 7.11 opcode abl abl description 00 b0l 01 b1l 10 a0l 11 a1l table 7.12 opcode rn rn (rn) description 000 r0 001 r1 010 r2 011 r3 100 r4 101 r5 table 7.13 opcode rn* rn* (rn*) description 000 r0 001 r1 010 r2 011 r3 100 r4 101 r5 110 rb 111 y
instruction opcode bit coding 7-205 table 7.14 opcode mod mod description 00 no modi?cation 01 +1 10 -1 11 +step table 7.15 opcode w w (rj) description 0r4 1r5 table 7.16 opcode reg/reg reg description reg description 00000 r0 10000 b0h 00001 r1 10001 b1h 00010 r2 10010 b01 00011 r3 10011 b11 00100 r4 10100 ext0 00101 r5 10101 ext1 00110 rb 10110 ext2 00111 y 10111 ext3 01000 st0 11000 a0 01001 st1 11001 a1 (sheet 1 of 2)
7-206 instruction set 01010 st2 11010 a01 01011 p / ph 11011 a11 01100 pc 11100 a0h 01101 sp 11101 a1h 01110 cfgi 11110 lc 01111 cfgj 11111 sv table 7.17 opcode ii ii description 00 no modi?cation 01 +1 10 -1 11 +step table 7.18 opcode jj jj description 00 no modi?cation 01 +1 10 -1 11 +step table 7.16 opcode reg/reg (cont.) reg description reg description (sheet 2 of 2)
instruction opcode bit coding 7-207 table 7.19 opcode qq qq (ri) description 00 r0 01 r1 10 r2 11 r3 table 7.20 opcode cond cond description cond description 0000 true 1000 c 0001 eq 1001 v 0010 neq 1010 e 0011 gt 1011 l 0100 ge 1100 nr 0101 lt 1101 niu0 0110 le 1110 iu0 0111 nn 1111 iu1 x dont care table 7.21 opcode x x description x dont care
7-208 instruction set table 7.22 opcode bank in banke instructions bank description 0001 cfgi 0010 r4 0100 r1 1000 r0 table 7.23 opcode ext ext description 010 ext0 011 ext1 110 ext2 111 ext3 table 7.24 opcode bbbb bbbb bit number bbbb bit number 0000 0 1000 8 0001 1 1001 9 0010 2 1010 10 0011 3 1011 11 0100 4 1100 12 0101 5 1101 13 0110 6 1110 14 0111 7 1111 15
8-1 chapter 8 on-chip emulation module (ocem) this chapter describes the on-chip emulation module (ocem), which is an optional module for debug support with the CWDSP1650. this chapter covers all aspects of the operation and interface of the ocem. this chapter contains the following sections: section 8.1, ocem overview section 8.2, ocem programming model section 8.3, ocem signals section 8.4, ocem breakpoints 8.1 ocem overview the ocem is an optional module that can provide on-chip emulation for a CWDSP1650-based chip. the ocem uses the bi/trap breakpoint of the CWDSP1650 core to implement all emulation functions. the ocem includes the following features: breakpoint generation program ?ow tracing scanice debug support suspended mode operation 8.1.1 breakpoint generation prede?ned conditions programmed into the ocem registers determine the breakpoint generation conditions. once a condition is met, the ocem activates the breakpoint mechanism (bi/trap), causing the core to
8-2 on-chip emulation module (ocem) suspend any current action and jump to the bi/trap interrupt vector. the ocem provides multiple breakpoints: program address breakpoints with separate counters data address breakpoint data value breakpoint combined data address and data value breakpoints external registers breakpoint abort breakpoint branch instruction breakpoint block repeat loop breakpoint interrupt breakpoint illegal access breakpoint program ?ow trace buffer full breakpoint single step breakpoint see section 8.4, ocem breakpoints, for more information about using these ocem breakpoints. 8.1.2 program flow tracing program ?ow tracing produces a dynamic record of program addresses that may be used for debugging a program. these addresses provide a full program trace of instructions executed by the core. the ocem contains a 16-bit program ?ow trace register and a 17-bit fifo program ?ow trace buffer, both are described in more detail in section 8.2.8, program flow trace register and program flow trace buffer. 8.1.3 scanice debug support to minimize chip pin count of a design, the ocem is designed to support the scanice serial testing and debugging interface. it also allows an external scan controller to take control of a debugging session without the need for the core to run a monitor program. see chapter 9, scanice, for more information.
ocem programming model 8-3 8.1.4 suspended mode operation the ocem supports a low power suspended mode. when in this mode, the ocem consumes negligible power and is effectively disabled. in the suspended mode, nothing inside the ocem is clocked. therefore, the ocem can be incorporated into ?nal designs with little penalty in terms of silicon area and power consumption. this enables the designer to debug a design in its ?nal form without the need for a special debugging prototype. 8.2 ocem programming model this section describes the ocem programming model. all registers and counters within the model are memory-mapped into the data memory space of the CWDSP1650 core. table 8.1 lists these components with their address locations and page numbers. table 8.1 ocem programming model register or counter physical address page status 0 register 0xf7ff 8-4 status 1 register 0xf7fe 8-6 mode register 0xf7fd 8-7 data address breakpoint 0xf7fb 8-9 data address mask 0xf7fa 8-9 program address breakpoint counter 3 0xf7f9 8-10 program address breakpoint counter 2 0xf7f8 8-10 program address breakpoint counter 1 0xf7f7 8-10 program address breakpoint 3 0xf7f3 8-10 program address breakpoint 2 0xf7f2 8-10 program address breakpoint 1 0xf7f1 8-10 program flow trace register 0xf7f0 8-10
8-4 on-chip emulation module (ocem) the ocem registers do not have to be memory mapped in systems using the scanice debug as the mapping is implemented in off-core logic. apart from the two status registers, the content of all the ocem registers and counters after a reset depends on the dbg_pin input. if dbg_pin is asserted high on the falling edge of rst, their contents before reset are preserved. otherwise, they are all cleared to zero. the same rule also applies to the program ?ow trace buffer. the two status registers are always cleared to zero after reset. the rest of this section describes the registers and counters from table 8.1 in more detail. 8.2.1 status 0 register the status 0 register contains status information for different breakpoints. the ocem updates this register automatically to re?ect the current breakpoint status when the core is not servicing a trap/bi interrupt. while servicing a trap/bi interrupt, this register is modi?ed only when written to explicitly. the status 0 register is located at address 0xf7ff. the value of this register after reset is zero. the core can read and write all bits in the register unless otherwise stated. figure 8.1 shows the bit ?elds for the ocem status 0 register. figure 8.1 status 0 register sft software trap 15, r the ocem sets this bit to one when it detects a software trap. a software trap occurs when the core executes the trap instruction. ill illegal breakpoint 14, r/w the ocem sets this bit to one when it detects an illegal breakpoint. an illegal breakpoint occurs when the program attempts an access to the mailbox space or ocem registers outside a breakpoint handler. tbf trace buffer full 13, r/w the ocem sets this bit to one when it detects a program ?ow trace buffer full breakpoint. 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 sft ill tbf int br res pa3 pa2 pa1 abort ereg cdva da dv
ocem programming model 8-5 int interrupt breakpoint 12, r/w the ocem sets this bit to one when it detects a breakpoint due to the core servicing an interrupt. br branch breakpoint 11, r/w the ocem sets this bit to one when it detects a branch or block repeat breakpoint. res reserved [10:8] these bits are reserved for lsi logic. these bits always read as zeroes. writing to these bits has no effect. pa3 program address 3 7, r/w when the ocem detects a program address breakpoint initiated by program address breakpoint register 3, pa3 is set to one. pa2 program address 2 6, r/w when the ocem detects a program address breakpoint initiated by program address breakpoint register 2, pa2 is set to one. pa1 program address 1 5, r/w when the ocem detects a program address breakpoint initiated by program address breakpoint register 1, pa1 is set to one. abort abort 4, r/w when the ocem detects a breakpoint due to its event input signal, abort is set to one. ereg external register 3, r/w the ocem sets this bit to one when it detects a breakpoint due to an user-de?ned register transaction supported by the CWDSP1650 core. cdva combined data value and address breakpoint 2,r/w when the ocem detects a breakpoint due to both a data value match and a data address match, cdva is set to one. da data address breakpoint 1, r/w the ocem sets this bit to one when it detects a breakpoint due to a data address match.
8-6 on-chip emulation module (ocem) dv data value breakpoint 0, r/w when the ocem detects a breakpoint due to a data value match, it sets dv to one. 8.2.2 status 1 register the status 1 register contains miscellaneous status information. the ocem updates this register automatically to re?ect the current status. unless otherwise stated, the core can read and write all bits in the register. the status 1 register is located at address 0xf7fe. value held at each bit after reset is described below. figure 8.2 shows the bit ?elds for ocem status 1 register. figure 8.2 status 1 register dbg debug 15, r/w a one on this bit indicates debug mode. the ocem sets dbg to one when the dbg_pin input is asserted on the falling edge of rst. boot boot 14, r/w a one on this bit indicates boot mode. the ocem sets boot to one when the boot_pin input is asserted on the falling edge of rst. err error 13, r/w the ocem sets this bit to one when a reset occurs during a breakpoint service routine. in this case, the emulation session might continue improperly after the reset. for example, if reset occurs through a hardware signal and not through the CWDSP1650 debugger, the core to debugger communication might be suspended inde?nitely, so a new emulation session must be initiated. mvd movd 12, r/w when the ocem detects the core executing a movd instruction, it sets this bit to one. 15 14 13 12 11 1 0 dbg boot err mvd res trei
ocem programming model 8-7 res reserved [11:1] these bits are reserved for lsi logic. these bits always read as zeroes. writing to these bits has no effect. trei trace entry indication 0, r trei acts as a tag bit for the current program ?ow trace buffer entry. refer to section 8.2.8, program flow trace register and program flow trace buffer, for details of the program ?ow trace buffer. 8.2.3 mode register the mode register contains bits that enable various ocem functions, such as breakpoints and single stepping. the core can read and write all mode register bits. the mode register is located at address 0xf7fd. the content of this register after reset depends on the input signal dbg_pin. if dbg_pin is asserted high on the falling edge of rst, the register content before reset is preserved. otherwise, all bits are cleared to zero. note that the ocem is prevented from raising any breakpoint while the core is servicing a trap/bi interrupt, regardless of the content of the mode register. figure 8.3 shows the bit-?elds for the ocem mode register. figure 8.3 mode register sse single step enable 15, r/w setting this bit to one enables single-step operation. ille illegal enable 14, r/w setting this bit to one enables a breakpoint on an illegal condition (for example, trying to access an ocem register not through the trap handler). bkre block repeat enable 13, r/w setting this bit to one enables a breakpoint when returning to the beginning of a block repeat loop. executing a rep loop will not raise this breakpoint. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sse ille bkre tbfe inte bre p3e p2e p1e extre extwe cdvae dare dawe dvre dvwe
8-8 on-chip emulation module (ocem) tbfe trace buffer full enable 12, r/w setting this bit to one enables a breakpoint when the program ?ow trace buffer is full. inte interrupt enable 11, r/w setting this bit to one enables a breakpoint upon detection of the servicing of an interrupt. bre br enable 10, r/w setting this bit to one enables a breakpoint when the core executes a branch-type instruction. a branch-type instruction could be one of the following: br, brr, call callr, calla, ret, retd, rets, reti, retid, or any instruction that has the program counter register (pc) in the core as a destination. p3e p3 enable 9, r/w setting this bit to one enables program address breakpoint 3. a breakpoint occurs when the core fetches an instruction from a program address speci?ed at program address breakpoint register 3 (address 0xf7f3). p2e p2 enable 8, r/w setting this bit to one enables program address breakpoint 2. a breakpoint occurs when the core fetches an instruction from a program address speci?ed at program address breakpoint register 2 (address 0xf7f2). p1e p1 enable 7, r/w setting this bit to one enables program address breakpoint 1. a breakpoint occurs when the core fetches an instruction from a program address speci?ed at program address breakpoint register 1 (address 0xf7f1). extre external register read enable 6, r/w setting this bit to one enables a breakpoint as a result of a user-de?ned register read transaction. extwe external register write enable 5, r/w setting this bit to one enables a breakpoint as a result of a user-de?ned register write transaction.
ocem programming model 8-9 cdvae combined data value and address enable 4, r/w setting this bit to one enables a breakpoint as a result of a simultaneous data address and data value match. dare data address read enable 3, r/w setting this bit to one enables data address breakpoints for data read transactions. a break occurs when the core reads from a data address location that matches the address in the data address breakpoint register. dawe data address write enable 2, r/w setting this bit to one enables data address breakpoints for data write transactions. a break occurs when the core writes to a data address location that matches the address in the data address breakpoint register. dvre data value read enable 1, r/w setting this bit to one enables a data value breakpoint on a data read transaction when the value read matches the data value breakpoint register (dvm) within the core. dvwe data value write enable 0, r/w setting this bit to one enables a data value breakpoint on a data write transaction when the value written matches the data value breakpoint register (dvm) within the core. 8.2.4 data address breakpoint register the data address breakpoint register is a 16-bit register containing the data address location that triggers a data address breakpoint. this register is located at address 0xf7fb. the core can read and write this register. the content of this register after reset depends on the input signal dbg_pin. if dbg_pin is asserted high on the falling edge of rst, the register content before reset is preserved. otherwise, all bits are cleared to zero. 8.2.5 data address mask register the data address mask register is a 16-bit register containing the data address mask. this register is located at address 0xf7fa. the core can read and write this register. a one on any bit in this register masks out the corresponding bit when matching the data address breakpoint register with the current data address on the xab and the yab. the
8-10 on-chip emulation module (ocem) content of this register after reset depends on the input signal dbg_pin. if dbg_pin is asserted high on the falling edge of rst, the register content before reset is preserved. otherwise, all bits are cleared to zero. 8.2.6 program address breakpoint counters the ocem has three 16-bit read/write program address breakpoint counters. each counter has a corresponding program address breakpoint register (see section 8.2.7, program address breakpoint registers. ) when a program address breakpoint is enabled, the ocem decrements a counter by one every time there is a valid program fetch address on the instruction address bus (iab) that matches the address in the corresponding program address breakpoint register. the counter stops decrementing when it reaches zero. the contents of these counters after reset depends upon the input signal dbg_pin. if dbg_pin is asserted high on the falling edge of rst, the content of the counters before reset are preserved. otherwise, the counters are cleared to zero. 8.2.7 program address breakpoint registers the ocem has three 16-bit read/write program address breakpoint registers containing the address locations that triggers program address breakpoints. when enabled, the ocem raises a program address breakpoint if a valid instruction fetch address on the iab matches the content of any one of these registers and the current value held in the corresponding program address breakpoint counter is either zero or one. the contents of these registers after reset depend on the input signal dbg_pin. if dbg_pin is asserted high on the falling edge of rst, the contents of the registers before reset are preserved. otherwise, the registers are cleared to zero. 8.2.8 program flow trace register and program flow trace buffer the ocem has a 16-bit program flow trace register and a 16-stage, 17-bit wide fifo program flow trace buffer. the buffer dynamically holds the most recent nonlinear program addresses, which are locations of instructions that cause discontinuity in the sequential program ?ow. examples of these instructions include branches and interrupts. the nonlinear addressees are stored in the program ?ow trace buffer in the order of their occurrence. each 17-bit entry in the trace buffer consists
ocem programming model 8-11 of a 16-bit nonsequential address and a tag bit. when set to zero, this tag bit identi?es entries that need to be decoded with adjacent entries. the entire graph of the program ?ow can be reconstructed by applying the recorded nonlinear addresses to the program source ?le containing instruction address information. the trace buffer reduces the volume of addresses that need to be kept to accurately reconstruct the program ?ow. the core cannot write to the program flow trace buffer, but it can read the buffer indirectly by reading the program flow trace register. this register re?ects the address ?eld of the current output of the fifo trace buffer. reading this register causes the next entry in the buffer to become the current output. the contents of the register and the buffer after reset depend on the input signal dbg_pin. if dbg_pin is asserted high on the falling edge of rst, the contents of the register and the buffer before reset are preserved. otherwise, they are cleared to zero. the trace buffer methodology uses the following principles: only taken branches, or nonsequential program fetches, are recorded. if the nonsequential instruction has a distinct destination (for example: br, brr, call, or callr), only the instruction address is recorded. if the nonsequential instruction does not have a distinct destination, both the instruction address and the target address are recorded. these include the instructions calla, ret, reti, retd, retid, rests, and any instruction with the pc register as a destination. note that mov ##long_immediate, pc is also in this group although it has a distinct target. interrupts are treated as nonsequential instructions. however, they can occur anywhere. although the target (destination) is known, the source, the last instruction being executed prior to the service routine, cannot be easily derived. therefore, the source address (the last instruction being executed before servicing the interrupt) and the destination address (the vector address) are both kept within the trace buffer. nonsequential addresses within the breakpoint handler are not recorded (including the br instruction that is at the trap vector address).
8-12 on-chip emulation module (ocem) nonsequential fetches that are due to the trap instruction are not recorded. the read address of a movp instruction and the write address of a movd instruction are not recorded although they appear on the iab. they are not used for fetching program instructions and do not affect the normal sequential program ?ow. 8.2.8.1 program flow trace buffer reading and decoding when reconstructing the program ?ow recorded in the program flow trace buffer, alternate reading of the trei bit in the status 1 register and the program flow trace register is required. the trei bit is always read ?rst as reading the program flow trace register causes the next entry in the buffer to become its current output. both registers should be read 16 times to ?ush the entire buffer. each pair of values read from the two registers represent one entry in the trace buffer. program ?ow reconstruction should start from the last entry read and proceed backwards. an entry with the tag bit set to one is a single entry record that contains the source address of an instruction causing a nonsequential program ?ow to a distinct target location. an entry with the tag bit set to zero is part of a double entry record recording a nonsequential program ?ow without a distinct target location. in a double word record, the ?rst entry contains the source address which is the location of the instruction that caused the branch. the second entry in the record contains the target address of the branch. figure 8.4 shows a program fragment with corresponding trace buffer entries. the ?rst few entries read from the trace buffer might have all bits set to one. these entries are not used since the buffer was last ?ushed. they contain no useful information and can be safely ignored. when the mvd bit in the ocem status 1 register is set to one, the integrity of the program ?ow trace cannot be guaranteed. this is because the core has executed a movd instruction, which might have modi?ed the program code.
ocem programming model 8-13 figure 8.4 program flow trace with corresponding trace buffer entries (a) program fragment . . . loc1:call ##loc2 ;distinct target location, single-entry record: a . . . loc2:mov ##loc5, a1l loc3:callaa1l ;nondistinct target location, two-entry record: b,c . . . loc 4:ret ;nondistinct target location, two-entry record: f,g . . . loc 5:ret ;nondistinct target location, two-entry record: d,e . . . out 1 loc1 a b 0 loc3 c 0 loc5 d 0 loc5 e 0 loc3 & 2 f 0 loc4 g 0 loc1 & 2 . . . . . . tag bits address in (b) flow trace buffer
8-14 on-chip emulation module (ocem) 8.3 ocem signals this section de?nes the ocem signals, which are organized according to function in the following subsections: section 8.3.1, service interface section 8.3.2, boot logic interface section 8.3.3, core memory bus interface section 8.3.4, user-de?ned register interface section 8.3.5, illegal access interface section 8.3.6, core control interface section 8.3.7, breakpoint interface section 8.3.8, scanice interface section 8.3.9, clocking and miscellaneous ocem signals table 8.2 lists all ocem and monitored CWDSP1650 core signals. table 8.2 ocem signal list interface signal mnemonic signal name input/ output service interface sv_a[3:0] service address bus input sv_di[15:0] service data bus in input sv_do[15:0] service data bus out output sv_g service chip select input sv_r service read enable input sv_w service write enable input boot logic interface boot_en boot mode enable output boot_pin boot pin input dbg_en debug mode enable output dbg_pin debug pin input urst_pin user reset pin input (sheet 1 of 3)
ocem signals 8-15 core memory bus interface iab[15:0] program address bus input pren program read enable input pwen program write enable input xab[15:0] x-memory address bus input xren x-memory read enable input xwen x-memory write enable input yab[15:0] y-memory address bus input yren y-memory read enable input ywen y-memory write enable input user-de?ned register interface ld_ext_reg external register write enable input rd_ext_reg external register read enable input illegal access interface ille illegal breakpoint enabled output illegal_access illegal access input core control interface blockloop block-repeat detected input branching branch detected input bti_service bi/trap service active input clr_istat clear interrupt status input dvm data value match input int_seen interrupt indication input invalid_pa invalid program address input mvd_exec move data-to-program detected input sel_trace[1:0] select address for trace input trace_tag trace tag input trace_unwrite trace unwrite input trace_write trace write input trap_service trap service indicator input table 8.2 ocem signal list (cont.) interface signal mnemonic signal name input/ output (sheet 2 of 3)
8-16 on-chip emulation module (ocem) 8.3.1 service interface this section describes the signals that support the ocem service interface. the service interface exists to imitate a static ram style interface, which eases ocem interfacing with other CWDSP1650 modules. the service interface occupies 16 memory address locations which can be mapped to anywhere in the data memory space. (note that the CWDSP1650 debugger assumes the ocem is mapped to locations 0xf7f0 C 0xf7ff when using cdi debug.) sv_a[3:0] service address bus input sv_a is a four-bit address bus selecting an ocem register or counter for access. breakpoint interface bi breakpoint interrupt output iack_bi breakpoint interrupt acknowledge input scanice interface scan_alert scan breakpoint alert output ext_start_scan external start scan output ocem_scan_alert ocem scan alert output scan_en scan enable input scanice_en scanice enable input scan_in scan chain input input scan_out scan chain output output scan_ws scan write strobe input test test mode input clocking and miscellaneous ocem signals ld_cc load clock control register input event external event input rst reset input second_cycle second cycle indicator input suspend ocem suspended mode enable input table 8.2 ocem signal list (cont.) interface signal mnemonic signal name input/ output (sheet 3 of 3)
ocem signals 8-17 sv_di[15:0] service data bus input sv_di is a 16-bit data input bus through which the ocem registers and counters are written. sv_do[15:0] service data bus output sv_do is a 16-bit data output bus through which the ocem registers and counters are read. sv_g service chip select input assert sv_g high when accessing the ocem. sv_r service read enable input assert sv_r high to read from the ocem. sv_w service write enable input assert sv_w high to write to the ocem. 8.3.2 boot logic interface this section describes the ocem signals that interact with the boot logic in a CWDSP1650 design. the ocem samples the input signals in this section only on the falling edge of rst when returning from a reset operation. note that the boot mechanism is always implemented off-core in a CWDSP1650 design. signals described in this section are most likely to be connected to off-chip strap pins and to the off-core boot logic. boot_en boot mode enable output the ocem drives this signal high when the boot bit in the status 1 register is set to one, which indicates to off-core boot logic that the boot mode is enabled. boot_pin boot pin input asserting this signal high on the falling edge of rst sets the boot bit to one in the status 1 register. connecting this signal to an off-chip strap pin allows off-chip control of program boot loading. dbg_en debug mode enabled output the ocem drives this signal high when the dbg bit in status 1 register is one indicating debug mode to the boot logic. dbg_pin debug pin input asserting this signal high on the falling edge of rst sets the dbg bit to one in the status 1 register.
8-18 on-chip emulation module (ocem) connecting this signal to an off-chip strap pin allows off- chip control of on-chip debugging logic. for example, the CWDSP1650 debugger forces a combined boot and debug mode to boot load a monitor program. urst_pin user reset pin input asserting this signal high on the falling edge of rst sets the err bit to one in status 1 register. note that this signal does not trigger a reset. instead, it is intended to be used by the CWDSP1650 debugger to detect a reset caused by an external event. for example, a user pushed an on-board reset button while the monitor program is running. in this case, the reset button should assert both rst and urst_pin. 8.3.3 core memory bus interface this section describes the ocem interface to the memory buses of the core. the ocem monitors these core signals to trigger the ocem program and data breakpoints. iab[15:0] program address bus input the core drives this 16-bit bus with the memory address of either the program instruction or the program data. pren program read enable input the core drives this signal high to request program data. pwen program write enable input the core drives this signal high to indicate a write to the program memory space. xab[15:0] x-memory address bus input the core drives this 16-bit bus with the x-memory space address. xren x-memory read enable input the core drives this signal high to request data from the x-memory address speci?ed by xab[15:0]. xwen x-memory write enable input the core drives this signal high to indicate a x-memory data write to the address speci?ed by xab[15:0].
ocem signals 8-19 yab[15:0] y-memory address bus input the core drives this 16-bit bus with the y-memory space address. yren y-memory read enable input the core drives this signal high to request data from the y-memory address speci?ed by yab[15:0]. ywen y-memory write enable input the core drives this signal high to indicate a y-memory data write to the address speci?ed by yab[15:0]. 8.3.4 user-de?ned register interface this section describes signals driven by the core to access user-de?ned registers. the ocem monitors these core signals to trigger the ocem external register breakpoints. ld_ext_reg external register write enable input the core drives this signal high during a user-de?ned register write cycle. rd_ext_reg external register read enable input the core drives this signal high during a user-de?ned register read cycle. 8.3.5 illegal access interface these ocem signals connect to a bus interface unit (biu) to provide program protection from illegal memory accesses. the ocem triggers an illegal breakpoint when it detects an illegal access. ille illegal breakpoint enabled output when the ille bit of the mode register is set to one, the ocem drives this signal high to indicate that the illegal access breakpoint is enabled. illegal_access illegal access input the biu drives this signal high to inform the ocem that an illegal access has occurred (such as an attempt to access the ocem registers not through the trap interrupt service routine).
8-20 on-chip emulation module (ocem) 8.3.6 core control interface this section describes the core control signals that the ocem decodes to monitor various core activities. blockloop block-repeat detected input the core drives this signal high whenever it detects a block-repeat loop returning to its start address from its end address (completing one loop.) branching branch detected input the core drives this signal high whenever a a branch- type instruction causes a nonsequential program ?ow. bti_service bi/trap service active input the core asserts this signal high upon execution of a trap/bi service routine. clr_istat clear interrupt status input the core asserts this signal high when it services an interrupt. dvm data value match input the core asserts this signal high to indicate a match between the content of the dvm register and the current value on the core internal data bus. int_seen interrupt indication input the core asserts this signal high when it is preparing to service an interrupt. invalid_pa invalid program address input the core asserts this signal high when it is not using the current address on the iab to fetch an instruction. this occurs when the core executes the movd and movp instructions to write or read the program memory. mvd_exec move data-to-program detected input the core asserts this signal high after it executes a movd instruction. the ocem logs this event to indicate potential corruption of program memory.
ocem signals 8-21 sel_trace[1:0] select addresses for trace input the ocem keeps a record of the last four addresses on the iab, including the current address. the core uses sel_trace[1:0] to specify which of these address values is selected to be written to the ocem trace buffer. trace_tag trace tag input the core asserts this signal high to indicate that the current program address is one of two addresses stored for certain nonsequential program ?ow operations. the ocem stores the value of trace_tag with the trace address values in the trace buffer. trace_unwrite trace unwrite input the core drives this signal high to unwrite the last trace address from the trace buffer. an unwrite capability is needed to erase a conditional branch trace buffer entry when the branch is not taken. trace_write trace write input the core drives this signal high to write an entry into the trace buffer. trap_service trap service indicator input the core drives this signal high when a software trap occurs. 8.3.7 breakpoint interface this section describes the ocem signals interfacing with the breakpoint interrupt logic of the core. bi breakpoint interrupt output the ocem asserts this signal high to send a breakpoint interrupt to the core. iack_bi breakpoint interrupt acknowledge input the core asserts this signal high to acknowledge a breakpoint interrupt sent by the ocem.
8-22 on-chip emulation module (ocem) 8.3.8 scanice interface this section describes the ocem signals that support the scanice interface. ext_start_scan external start scan input the scanice interface asserts this signal high to force a breakpoint interrupt allowing the scan controller to take control of the CWDSP1650 core. ocem_scan_alert ocem scan alert output the ocem asserts this signal when the core jumps to the bi/trap vector address while in scanice mode, which indicates that the scanice mode has been entered. scan_en scan enable input the scanice interface asserts this signal high to con?gure all registers in the ocem scan chain in serial scan mode. scanice_en scanice enable input this signal is asserted high to con?gure the ocem for scanice debug. scan_in scan chain input input this input signal connects directly to the test input of the ?rst ?ip-?op in the ocem scan chain. scan_out scan chain output output this output signal connects directly to the test output of the last ?ip-?op in the ocem scan chain. scan_ws scan write strobe input asserting this signal high disables all write strobe memory signals from the core. disabling all core write transactions protects the contents of the off-core rams during scan mode. test test mode input when scan_en is low, driving test high forces all registers in the ocem scan chain to be load enabled, implementing a capture function when in scan mode. test should also be asserted whenever scan_en is asserted.
ocem signals 8-23 8.3.9 clocking and miscellaneous ocem signals this section describes the clocking and miscellaneous signals of the ocem. ld_cc load clock control register input this external input signal is the strobe for loading the clock control register. this signal has a lower priority than the start_scan or stop_scan signals and should not be used as a substitution for either of these signals (by writing 0b1111 or 0b0000 to the ccu register.) ocem_clk ocem clock input the CWDSP1650 ccu drives this signal to provide a clock to the ocem. the ocem_clk is extended by wait states, as the core_clk is. event external event input off-core glue logic drives this signal high to initiate an abort breakpoint. rst reset input driving this signal high resets the ocem. second_cycle second cycle indicator input off-core glue logic (normally a biu) asserts this signal high for two icu_clk cycles when the core comes out of a reset. suspend ocem suspended mode enable input asserting this signal high forces the ocem into suspended mode, which ensures that the ocem registers are not clocked. in suspended mode the ocem consumes negligible power and is effectively isolated from the other CWDSP1650 modules.
8-24 on-chip emulation module (ocem) 8.4 ocem breakpoints this section describes the operations of different ocem breakpoints. the breakpoints available for the ocem are: program address data address data value combined data address and data value external register abort illegal access branch block repeat interrupt single step program ?ow trace buffer full 8.4.1 program address breakpoint the ocem supports three program address breakpoints. each breakpoint has three controlling components: a program address breakpoint register to hold the breakpoint address a program address breakpoint counter that holds the number of matches needed until a breakpoint is issued an enable bit in the mode register
ocem breakpoints 8-25 table 8.3 lists these three breakpoints and components. for more information on any of these counters or registers, see section 8.2, ocem programming model. when the core fetches an instruction, the ocem detects a match between the address appearing on the instruction address bus (iab) and an address in any of the program address breakpoint registers. if a match with any of the registers occurs while the corresponding program address breakpoint is enabled, the ocem decrements the appropriate breakpoint counter by one. the ocem also triggers a breakpoint if the match occurs when the value held by the counter is one or zero. a counter stops decrementing once it reaches zero. a program address breakpoint stops a program at the speci?ed location. the instruction at that location is not executed until after the breakpoint is serviced. the ocem ignores addresses on the iab that are not used for valid program instruction fetches. to cause a breakpoint on every occurrence of a program address, the address counter should be set to either zero or one. to cause a breakpoint on the n th occurrence only, the counter should be set to n. writing zeros to the p1e , p2e, and p3e bits within the ocem mode register disables the program address breakpoints. the pa1, pa2, and pa3 bits in the status 0 register indicate the source of the program address breakpoint. table 8.3 program address breakpoint components program address breakpoint # program address breakpoint register program address breakpoint counter mode register enable bit 1 1 1 pe1 2 2 2 pe2 3 3 3 pe3
8-26 on-chip emulation module (ocem) 8.4.2 data address breakpoint a data address breakpoint occurs on a match between the ocem data address register and the CWDSP1650 data address buses, xab and yab. the ocem sets the da bit in the status 0 register to one when it detects a data address breakpoint. the data address mask register allows the data address breakpoint to expand into an address space rather than a singular address. a one in any bit in this register masks the corresponding bit in the address match. a match occurs when all other bits in the data address register and the data address buses are equal. the data address breakpoints are separately enabled for read and write transactions. to break on read transactions, set the dare bit in the mode register to one. to break on write transactions, set the dawe bit in the mode register to one. a data address breakpoint is serviced on the completion of the data transaction causing the breakpoint. hence, the breakpoint is serviced at least two cycles after the prefetch of the instruction causing the breakpoint. depending on whether the instruction causing the breakpoint is followed by a multicycle instruction, up to two instructions are executed before the core executes the breakpoint service routine. 8.4.3 data value breakpoint the data value breakpoint is activated when the ocem detects a data match between the CWDSP1650 internal data bus and the contents of the dvm register. note that a data value breakpoint is due only to a matched data during memory transactions. the ocem sets the dv bit in the status 0 register to one when it detects a data value breakpoint. the data value breakpoint is separately enabled for read and write transactions. to break on read transactions, set the dvre bit in the mode register to one. to break on write transactions, set the dvwe bit in the mode register to one. a data value breakpoint is serviced on the completion of the data transaction causing the breakpoint. hence, the breakpoint is serviced at least two cycles after the prefetch of the instruction causing the breakpoint. depending on whether or not the instruction causing the
ocem breakpoints 8-27 breakpoint is followed by a multicycle instruction, up to two instructions can be executed before the core executes the breakpoint service routine. 8.4.4 combined data address and data value breakpoints to enable the ocem to detect combined data address and data value conditions, the cdvae bit in the mode register should be set to one. note that the dare and dvre bits and/or the dawe and dvwe bits must also be set to one for the ocem to detect a dual breakpoint condition. when a combination of data address and data value breakpoints is enabled, a breakpoint is triggered only when both a data value match and a data address match occur. a combined data address and data value breakpoint is serviced on the completion of the data transaction causing the breakpoint. 8.4.5 external register breakpoint an external register breakpoint occurs when the CWDSP1650 core accesses one of its four user-de?ned registers. the ocem sets the ereg bit to one in the status 0 register when it detects an external register breakpoint. the external register breakpoint is enabled separately for read and write transactions. to break on read transactions, the extre bit in the mode register is set to one. to break on write transactions, set the extwe bit in the mode register to one. an external register breakpoint is serviced on the completion of an external register transaction. 8.4.6 abort breakpoint an external breakpoint occurs when the event input of the ocem is asserted. the ocem registers the event input on the rising edge of ocem_clk. event should be synchronized with ocem_clk before entering the ocem. the abort breakpoint is always enabled. the ocem sets the abort bit of status 0 register when it detects this breakpoint.
8-28 on-chip emulation module (ocem) 8.4.7 illegal access breakpoint one feature of the ocem is to protect the reserved mail box area (addresses 0xf400 C 0xf7df) and the ocem registers (addresses 0xf7f0 C 0xf7ff) from illegal accesses. legal access of the mailbox and register spaces occur only through the breakpoint handler (the routine that is executed as a result of the trap/bi interrupt). attempting to access the mailbox or ocem space through anything other than the breakpoint routine causes a breakpoint and sets the ill bit to one in the status 0 register. the illegal breakpoint is enabled/disabled through the ille bit within the mode register. both the ille bit in the mode register and the ill bit in the status 0 register must be written to through the breakpoint handler. any other attempts to write to these bits are disabled. the illegal breakpoint mechanism also protects the breakpoint handler routine from other illegal accesses, such as when a user program jumps into the breakpoint handler not through a trap/bi interrupt. in such a case, if the handler accesses the mailbox area, it will trigger an illegal breakpoint. 8.4.8 branch and block repeat breakpoints the ocem activates a branch breakpoint when it detects a branch-type instruction. a branch-type instruction could be one of the following: br, brr, call, callr, calla, ret, retd, rets, reti, retid, and any instruction that has the program counter register (pc) in the core as destination. the ocem activates a block repeat breakpoint when it detects the switch from the last to the ?rst address in a block repeat instruction (bkrep). no breakpoint is triggered when the core fetches the ?rst instruction for the ?rst time when entering the block repeat loop. the br bit in the mode register enables/disables the branch breakpoint. the bkre bit in the mode register enables/disables the block repeat breakpoint. the ocem sets the br bit in the status 0 register when it detects either a branch breakpoint or a block repeat breakpoint. note that the rep instruction does not cause a branch breakpoint. the breakpoint occurs for taken branches only. the next instruction executed after returning from the breakpoint service routine is at the target address. two exceptions are the brr and callr instructions, where the next instruction executed after returning from the breakpoint service routine is at the target address plus one.
ocem breakpoints 8-29 8.4.9 interrupt breakpoint an interrupt breakpoint occurs when the ocem detects the core is going to service one of four interrupts: int0, int1, int2, or nmi. the core services this breakpoint and then services the interrupt causing the breakpoint before returning control to the interrupted program. the ocem sets the int bit in the status 0 register to one when an interrupt breakpoint occurs. setting the inte bit in the mode register enables the interrupt breakpoint. 8.4.10 single-step operation setting the sse bit to one in the mode register enables single-step operation. in the single-step mode, the ocem automatically breaks after each instruction the core executes. the ocem does not set a speci?c status bit for a single-step breakpoint. 8.4.11 program flow trace buffer full breakpoint setting the tbe bit in the mode register to one enables the trace buffer full breakpoint. the ocem sets the tbf bit in the status 0 register to one when the trace buffer is full. the trace buffer is a 16-stage fifo buffer logging the most recent nonsequential operations. a nonsequential program ?ow can be recorded with one or two buffer entries. to prevent data loss due to an over?ow, the trace buffer full breakpoint is activated when the buffer has either 15 or 16 valid entries. once the whole trace buffer is read, the ocem ?lls it with all ones, thus isolating new incoming addresses from the old ones.
8-30 on-chip emulation module (ocem)
9-1 chapter 9 scanice this chapter describes the CWDSP1650 scan based in-circuit emulation (or scanice) implementation, which is an optional module for embedded debugging and emulation. this chapter covers the operation and interface of the CWDSP1650 scanice implementation. scan based in-circuit emulation (scanice) enables complete observation and control of circuit states for debug purposes through circuitry included in most devices for testing during manufacture. this technique allows the entire processor state to be clocked out of the design and, if desired, a modi?ed state to be clocked back in over a serial bus (or scan chain ) using a lower frequency clock. inserting a scan chain into a core design is normally performed by a scan insertion software tool as part of the design-for-test process. a major bene?t of the scanice approach is that very few package pins and additional logic are required to implement a comprehensive debugging system, thus removing the need for debug prototypes and reducing the failure risk for production silicon. this chapter contains the following sections: section 9.1, scanice power saving registers section 9.2, scanice requirements section 9.3, scanice interface section 9.4, CWDSP1650 scanice support section 9.5, memory access during scanice section 9.6, scanice reset this chapter describes scanice designs in general terms whenever possible, but uses the CWDSP1650 reference device design as an example when needed. if you do not recognize some of the scanice
9-2 scanice signal names, they are most likely reference device pins described in the CWDSP1650 reference device users guide . 9.1 scanice power saving registers figure 9.1 illustrates a power-saving, scan-inserted register bank. figure 9.1 power saving register with scan inserted there are two input pins that control its mode of operation, scan_en and test, that are common for every register on a particular scan chain scan_en scan_en gclk gclk test load enable clock d le* q scan_en
scanice power saving registers 9-3 and are routed to each ?ip-?op in the bank. table 9.1 lists the scanice operations enabled with the scan_en and test pins. during production testing, test data is ?rst shifted into the power saving registers using the serial scan mode. then a capture cycle forces every register to be clocked and load-enabled. the result of this capture cycle is then shifted out of the device and compared with the desired state. it is common for all registers of a design to be located on a single scan chain. in systems with signi?cant amounts of memory, an additional scan chain may be provided speci?cally for memory access. since the core will normally contain many thousands of register bits, the main scan chain could take many thousands of scan clock cycles to completely clock in/out of the chip. this is not signi?cant for core testing since the scan clock will usually be running at speeds in the order of 5 mhz. however, when the memory block ?lls and block reads or program loading is required, the scan delay time could become unacceptably long. a second and much shorter scan chain, dedicated for memory accesses, can be added to improve overall scan performance. in this scenario the core generates the addresses for memory accesses using its internal address registers while data is loaded to or read from the memory scan chain. in a typical CWDSP1650 system, scanice replaces the functionality provided by a software monitor program, by giving read/write access to core registers, ocem registers, and memory. the key difference is that a monitor program typically communicates this information through an off-chip bus to a memory mapped mailbox, while scanice utilizes a serial link to an off-chip scan controller. table 9.1 scanice operational modes test scan_en operation mode 0 0 normal x 1 serial scan 1 0 capture
9-4 scanice 9.2 scanice requirements during scan, when the contents of every ?ip-?op in a particular scan chain is serially shifted out of the device, the clock to each ?ip-?op is sourced by the off-chip scan controller. since this clock is different from the one used in normal operation, the clock-controller must stop and switch clocks before scanning can begin. it is important that when the main clock is stopped, the core is in a stable state; all data that a programmer expects to be stored in the registers is stored, and the core is not in the middle of a wait-stated access to memory or off-chip peripherals. to achieve this condition, the CWDSP1650 enters scan mode only when it has just executed a breakpoint interrupt or software trap. by ensuring that two nops are read from the interrupt service vector, the clock can be stopped cleanly while executing these instructions, guaranteeing the state of the pipeline. proper operation of the ocem is integral to the functioning of scanice. a block diagram of a typical con?guration including the core, ocem, and scanice supporting circuitry is illustrated in figure 9.2 .
scanice requirements 9-5 figure 9.2 scanice support in a CWDSP1650 system the following sections describe the functionality of the main blocks of figure 9.2 that control the operation of scanice. it is noted that although the CWDSP1650, ccu and ocem are supplied as hard-macros, the scan interface logic and scan memory interface are application dependent and must be designed speci?cally into each target system. scan interface logic start_scan stop_scan ext_start_scan ocem_scan_alert memory control bti_service ccu ocem CWDSP1650 scan memory interface memory and external registers core_clk ocem_clk bi dbg_pin boot_pin scanice_en edb (core) edb data buses six-pin scan interface second_cycle master scan_clk core
9-6 scanice 9.3 scanice interface table 9.2 details the six-wire bus between the scan interface and the off- chip scan controller in figure 9.2 as implemented in the CWDSP1650 reference device. for a more detailed description of these signals (pins), please refer to the CWDSP1650 reference device users guide . this six-pin interface serially loads the scan control register, which controls all scanice operations while the CWDSP1650 is in the serial scan mode. for more information on the scan control register, see section 9.3.1, scan control register. scan interface logic details are design dependent, but a block diagram of an example circuit is shown in figure 9.3 . the main elements from the ?gure are further described in the following subsections. table 9.2 six-pin scanice interface signal input / output to asic function ext_scan_in input serial scan data input ext_scan_out output serial scan data output ext_scan_ctrl input start of scan indication to on-chip scan interface scan_clk input scan clock input scan_alert output event indication output from scan controllers ext_scan_rst input resets on-chip scan control logic
scanice interface 9-7 figure 9.3 example scan interface 9.3.1 scan control register to program the scan control register, ?rst serially load the shadow register with ext_scan_in data clocked by scan_clk. then parallel load this shadow register data to the scan control register at the end of the programming sequence. this technique ensures that the control lines do not change state incorrectly during the serial information transfer. the shadow register is selected as the destination of the ext_scan_in signal whenever the ext_scan_ctrl signal is asserted. once all the required bits have been clocked into the shadow register, the ext_scan_ctrl signal is deasserted and the parallel load to the scan control register occurs on the second next edge of scan_clk. the length and function of the scan control register will vary with each application depending on the variety of functions scanice has to scan instruction register control logic 0 [9:1] [11:10] scanice control external scan logic control clock gating ext_scan_in ext_scan_ctrl scan_clk or or ext_scan_out scan reset pin shadow main reset scan logic reset scan logic controls scan clocks ocem_scan_alert scanice controls scan control register chain outputs ext_scan_rst
9-8 scanice perform. figure 9.4 shows the bit-?elds of an example CWDSP1650 scan control register. figure 9.4 scan control register stsc stop scan when asserted high this bit forces exit from scan mode. note that the ccu waits for this bit to be deasserted before restarting the CWDSP1650 clocks. ess external start scan when asserted high this bit asserts bi, allowing the off-chip scan controller to take control of the CWDSP1650. ccmr clock core and memory register when asserted high this bit routes scan_clk to both the CWDSP1650 and the memory interface logic. scne scan enable this bit con?gures the ocem for scanice debug and controls what happens when a breakpoint interrupt or trap is detected. btm boot mode this bit drives the boot_pin signal of the ocem. dbgm debug mode this bit drives the debug_pin signal of the ocem. edbc edb control in the scan memory interface logic, the source of the edb can be either the edb from the CWDSP1650 core or an internal 16-bit register loaded through the scan interface logic. edbc selects between either the edb or a 16-bit register for edb control. ffse scan flip-flop scan enable input this bit drives the scan enable input of every ?ip-?op on the scan chain selected by the scs bit. stsc ess ccmr scne btm dbgm edbc ffse fft scs mwd scrst
scanice interface 9-9 fft scan flip-flop test input this bit drives the test input of every ?ip-?op on the scan chain selected by the scs bit. scs scan chain select this bit selects between the available target scan chains. in the CWDSP1650 reference device, there are two scan chains in addition to the shadow register in the scan interface logic; the main scan chain and a 16-bit scan chain for the scan memory interface. in an application with more than two scan chains, scs may be a multi-bit ?eld. mwd memory write disable when asserted high, this bit disables all memory write enable signals, thus protecting the CWDSP1650 memory during scan operations. scrst scan control reset this bit connects to the reset signals of all CWDSP1650 logic blocks except the scan interface logic. this allows resetting of all CWDSP1650 components during a serial scan, without affecting the current scan operation. 9.3.2 scanice control the scanice control block in figure 9.3 controls the entry and exit from scan mode. there are several ways in which scan mode can be entered: hardware breakpoint software trap debug boot debug reset abort figure 9.5 shows an example entry into scan mode through an ocem breakpoint interrupt. this example is equally valid for any of the scan mode entry methods.
9-10 scanice figure 9.5 entry to scan using a breakpoint interrupt the assertion of ocem_scan_alert indicates entry into scan mode, but the triggering of the ocem bi signal differs. the ocem_scan_alert assertion is synchronous to bti_service when scanice_en is asserted. for hardware breakpoints and the software trap, bi is asserted in the usual way by the ocem and the core. the external scan controller initiates scan by asserting the ess bit in the scan control register, which drives the ext_start_scan signal from the scan interface. finally a debug boot initiates a breakpoint interrupt immediately following reset through dedicated circuitry in the ocem. following assertion of ocem_scan_alert, the scanice interface asserts ext_start_scan to control the ccu, asserts scan_flag to indicate entry into scan mode for on-chip logic and asserts scan_alert to inform the off-chip scan controller that it now has control of the CWDSP1650 and support logic. master core_clk iab idb bi iack_bi instr_reg bti_service ocem_scan_alert start_scan scan_flag scan_alert note: instr_reg - contents of the instruction register inside the CWDSP1650. 0104 0105 0106 0102 0002 0003 0004 4182 0102 5820 8de0 0000 0000 4182 0102 5820 8de0 0000
scanice interface 9-11 the only mechanism for leaving the scan mode is through the stsc bit in the scan control register. this bit must be set to one and cleared back to zero before the ccu clocks stopped during scan mode are started again. figure 9.6 shows the CWDSP1650 leaving scan mode through the stsc bit. figure 9.6 stop scan mode 9.3.3 external scan logic control each register on a destination scan chain has two inputs that control its operation; scan_en and test. the function of these signals is described in section 9.1, scanice power saving registers. the external scan logic control block drives the scan enable and test inputs of each scan chain depending on the state of the scne, fft, ccmr and scs bits of the scan control register. see section 9.3.1, scan control register, for more information on these bits. idb master stop_scan core_clk bti_service ocem_scan_alert scan_flag scan_alert iab instr_reg 0004 0102 0103 0104 0000 8de0 abab 4182 45c0 (reti) 8de0
9-12 scanice 9.3.4 clock gating it is often convenient to adjust which scan chains the scan-clock controls. this is handled by the clock gating block and con?gured with the ccmr and scs bits of the scan control register. see section 9.3.1, scan control register, for more information on these bits. 9.4 CWDSP1650 scanice support the ocem and ccu module both contain special features to assist the scanice interface. 9.4.1 ocem scanice support to support scanice, the ocem has the following features: a breakpoint interrupt is triggered when ext_start_scan from the scan interface is asserted. a breakpoint interrupt is triggered when boot_pin, dbg_pin, scanice_en, and second_cycle are asserted. this forces entry to scan mode during a debug-boot before any instructions are decoded. ocem_scan_alert is asserted whenever bti_service and scanice_en are asserted. all ocem registers are scan enabled, which allows hardware breakpoints to be set when in scan mode by the scan controller. 9.4.2 ccu scanice support the ccu has the following features to support scanice: scan_clk is multiplexed with master clock to source the main clock and during scan mode, scan_clk is routed to most output clocks. the start_scan and stop_scan signals control the switching to and from scan mode as indicated in figure 9.5 and figure 9.6 . the ccu controls the clean stopping and switching of clocks.
memory access during scanice 9-13 during scan mode, the state of the clock control register before entering scan mode is stored in a shadow register. this shadow register is scan enabled, allowing the resumption clock speed on leaving scan mode to be changed and the memory clock skews to be programmed. 9.5 memory access during scanice during a conventional debug when a monitor program runs on the core, access to memory is carried out in the same way as during normal operation. when in scan mode, this would involve preparing the core through the scan chain for a memory read/write operation and would thus require a complete scan for every data value. this is prohibitively slow when large blocks of data or program memory must be transferred between the debugger and a device. a faster approach is to provide an alternative scan enabled source for data to the edb and destination for the core input buses. by using a separate and much smaller scan chain, the time for accessing memory can be considerably reduced. figure 9.7 shows the support provided on the CWDSP1650 reference device for memory access.
9-14 scanice figure 9.7 example scanice memory access scheme a 16-bit register with its own 16-bit scan chain is located within the memory scan interface block; this register will be referred to as the memory register. the memory register output is multiplexed to the edb as determined by the edbc bit in the scan control register. in this way, the memory register can be quickly loaded during scanice, and the data presented to all on-chip memory blocks. the input to the memory register is derived from the data-buses entering the core; in figure 9.7 , just the memory data buses are shown. the input bus selected is determined by the various read enable control signals driven by the core. during a read or write memory access when in scan mode, the core is con?gured to supply the appropriate addresses and control signals for the memory. for contiguous blocks of data, the core internal address modi?cation circuitry can increment the presented address on successive clock cycles, thus avoiding the need to scan the core for every data value. for a memory read the memory register must be pram xram xdb idb ydb edb di di do do do di yram biu ad ad ad xab ya b iab ext_scan_out scan memory interface edbc CWDSP1650 core ext_scan_in
scanice reset 9-15 clocked to load the data being read, and the core must be clocked to update the address it is sourcing; this is the reason for the ccwr bit in the scan control register. 9.6 scanice reset a complication that arises when developing embedded core debug systems is handling a reset. there are numerous methods for triggering a reset, the most common being board-level push-buttons and debugger commands. on leaving reset it is often useful to be able to con?gure the device for a particular mode of operation (boot pin and debug pin, for example, that are driven to the ocem). on the CWDSP1650 reference device, strap or con?guration pins are brought out to the chip periphery, limiting the con?gurability and ?exibility of the pin-count. the scan control register offers a unique opportunity to extend the con?gurability of a device during debug without impacting the pin-count. this method is illustrated above by including the boot and debug pin bits in the scan control register, and can be extended to include other functions as needed. one of the problems with embedded debug is how to communicate to the debug software that a hardware reset has occurred. the ocem sets the err bit in status 1 register to one when a reset occurs during a breakpoint service routine. this tells the debugger that its view of the core state may be incorrect. this concept could be extended by including a bit in the scan interface control shadow register that is set during normal operation. when a reset occurs, this bit would be cleared and the next time the scan controller does anything it will see that a reset was executed since the last scan. this bit would then probably reset the device again, but also ensure that the scan control register was appropriately set up when releasing reset. for this reset scheme to work, it is required that the scrst bit in the scan control register not reset the scan control logic. this can be achieved as indicated in figure 9.3 . this scanice reset method makes it possible to ?rst reset the entire device through a reset pin, reset the device again with scrst, and guarantee both the state of the device and how it will be con?gured after reset.
9-16 scanice
10-1 chapter 10 speci?cations this chapter speci?es the physical and electrical characteristics of the CWDSP1650 dsp core. it contains the following sections: section 10.1, physical speci?cations section 10.2, ac timing diagrams 10.1 physical speci?cations table 10.1 lists the dimensions of the CWDSP1650 core in lsi logics g10 technology. 10.2 ac timing diagrams the CWDSP1650 can use various clocks for different operations. the clock control unit (ccu) selects the appropriate clock for the current transaction needs. speci?c information about the ccu and the clocks it generates can be found in section 6.7, clock control unit (ccu). the input setup time is de?ned from the signal valid to the rising edge of the clock and the input hold time is de?ned from the rising edge of the clock to the signal valid. for input setup times, the driver must drive the signal valid before any receivers need it. for input hold times, the driver must hold the signal valid longer than needed by any receiver. table 10.1 CWDSP1650 physical layout size core technology width height total area 1 1. this ?gure excludes power rings. CWDSP1650 g10 2.0 mm 2.5 mm 5.0 mm 2
10-2 speci?cations the output valid and invalid delay times are de?ned from the rising edge of the clock to the signal valid. the section is further divided into the following subsections: section 10.2.1, ocem registers section 10.2.2, data and program memory section 10.2.3, user-de?ned registers 10.2.1 ocem registers this section illustrates waveforms for reading and writing the ocem registers. the ocem registers are memory-mapped to location 0xf7f0 to 0xf7ff in the data memory space and can be accessed with or without wait states. the ocem provides a service interface to mimic a static ram interface that allows the ocem to interface with the core through a bus interface unit (biu) as a memory device. figure 10.1 and figure 10.2 show timing diagrams for writing and reading the ocem. table 10.2 lists the related timing values from these ?gures. figure 10.1 writing the ocem ocem_clk sv_di sv_g sv_w t sgi t sgv t sih t sis t sah t sas sv_a t swv t swi
ac timing diagrams 10-3 figure 10.2 reading the ocem table 10.2 ocem access timing constraints parameter timing constraint min (ns) max (ns) remark t sas sv_a setup 24 C required by ocem t sah sv_a hold C 1 required by ocem t sis sv_di setup 22 C required by ocem t sih sv_di hold C 1 required by ocem t sov sv_do valid 2 C C t soi sv_do invalid C 1.1 C t sgv sv_g valid C 1.6 required by ocem t sgi sv_g invalid 1 C required by ocem t srv sv_r valid C 1.6 required by ocem t sri sv_r invalid 1 C required by ocem t swv sv_w valid C 1.8 required by ocem t swi sv_w invalid 1.3 C required by ocem ocem_clk sv_d0 sv_g sv_r t srv t soi t sov sv_a t sri
10-4 speci?cations 10.2.2 data and program memory the ?gures in this section show the optional memory clocks, required for synchronous memory only. typically, a ccu generates these memory clocks to optimize performance in any application. the core facilitates optimal data memory clocking with the signal ram_wt. ram_wt is an early indicator of a write transaction with the data memory. in designs where the data memory is in the critical path, ram_wt can be used to turn off the data memory clock early in a read transaction cycle. note: to interface with asynchronous memory, external strobing logic might be required. the reminder of this section contains the following timing ?gures and tables: figure 10.3, data memory write access figure 10.4, data memory read access figure 10.5, program memory write access figure 10.6, program memory read access figure 10.7, memory access with wait state table 10.3, memory interface timing constraints figure 10.3 data memory write access write cycle t dai t dav t edv t edi t dcv t dci t dmsw core_clk xab/yab edb xwen/ywen dmem_clk* * required for synchronous memory only.
ac timing diagrams 10-5 figure 10.4 data memory read access figure 10.5 program memory write access read cycle t xs/tys t xh/tyh t dcv t dci t dmsr core_clk xab/yab xdb/ydb xren/yren dmem_clk* * required for synchronous memory only. write cycle t pai t pav t edv t edi t pcv t pci t pmsw core_clk iab edb pwen pmem_clk* * required for synchronous memory only.
10-6 speci?cations figure 10.6 program memory read access figure 10.7 shows the waveforms for a data memory read with one wait state. because the data read transaction has one wait state, wait_ctl is held asserted for one cycle. the address bus xab and the memory read enable xren are kept stable during the wait cycle. the machine cycle is effectively extended to two mclk cycles. the core reads the data from edb at the end of the second cycle. read cycle t is tih t pcv t pci t pmsr core_clk iab idb pren pmem_clk* * required for synchronous memory only.
ac timing diagrams 10-7 figure 10.7 memory access with wait state table 10.3 memory interface timing constraints parameter timing constraint min (ns) max (ns) remark t dav data address valid C 3.8 C t dai data address invalid 0 C C t edv external data valid C 8.6 C t edi external data invalid 0 C C t dcv data controls valid C 4.1 C t dci data controls invalid 0 C C t xs x data setup 9.7 C required by core. t xh x data hold 2 C required by core. t ys y data setup 9.7 C required by core. t yh y data hold 2 C required by core. (sheet 1 of 2) access cycle 1 wait state txs twh mclk core_clk xab xdb xren wait_ctl twl
10-8 speci?cations t pav program address valid C 10.2 C t pai program address invalid 0 C C t pcv program controls valid C 11.6 C t pci program controls invalid 0 C required by core. t is idb (program data) setup 1 C required by core. t ih idb (program data) hold 2 C required by core. t dmsw dmem_clk write skew 1 see note t dmsr dmem_clk read skew 2 see note t pmsw pmem_clk write skew 3 see note t pmsr pmem_clk read skew 4 see note t wh wait_ctl high setup 18.6 C required by core. t wl wait_ctl low setup 20.8 C required by core. 1. max(t dav ,t edv ,t dcv ) + memory setup 2. cycle time - t xs /t ys -1ns 3. max(t pav ,t edv ,t pcv ,) + memory setup 4. cycle time - t is-1ns table 10.3 memory interface timing constraints (cont.) parameter timing constraint min (ns) max (ns) remark (sheet 2 of 2)
ac timing diagrams 10-9 10.2.3 user-de?ned registers figure 10.8 shows the waveforms for both a user-de?ned register read and a user-de?ned register write. table 10.4 lists the timing constraints shown in this ?gure. figure 10.8 user-de?ned register access core_clk sel_ext_reg_rd edb ext_in[15:0] ld_ext_reg rd_ext_reg t lexi t lexv t rexv t rexi t exh t exs t edi t edv t seri t serv t sewi t sewv sel_ext_reg_wt
10-10 speci?cations table 10.4 user-de?ned register interface timing values parameter timing constraint min (ns) max (ns) remarks t sewv sel_ext_reg_wt valid C 1.3 C t sewi sel_ext_reg_wt invalid 1.3 C C t serv sel_ext_reg_rd valid C 1.3 C t seri sel_ext_reg_rd invalid 1.3 C C t edv external data valid C 8.6 C t edi external data invalid 0 C C t exs ext_in[15:0] setup 14 C required by core. t exh ext_in[15:0] hold 2 C required by core. t lexv ld_ext_reg valid C 1.5 C t lexi ld_ext_reg invalid 1.4 C C t rexv rd_ext_reg valid C 1.4 C t rexi rd_ext_reg invalid 1.4 C C
a-1 appendix a CWDSP1650 register summary this appendix contains a quick description of all the CWDSP1650 registers. table a.1 lists the CWDSP1650 registers, any abbreviations used in this manual, and a page number for the description of each. table a.1 CWDSP1650 registers functional block register name abbreviations reference page cbu registers ax accumulators (axe, axh, or axl) 4-3 bx accumulators (bxe, bxh, or bxl) 4-5 x register C 4-6 y register C 4-6 p register C 4-6 interrupt context swithing registers C 4-7 shift value register sv 4-9 daau registers address registers 0-5 r0-r5 4-10 con?guration registers cfgi, cfgj 4-11 base register rb 4-11 stack pointer register sp 4-12 alternative bank registers r0b, r1b, r4b, cfgib 4-12 min/max pointer latching register mixp 4-13 (sheet 1 of 2)
a-2 CWDSP1650 register summary pcu registers data value match register dvm 4-14 internal con?guration register icr 4-14 program counter pc 4-15 loop counter lc 4-15 status registers status register 0 st0 4-16 status register 1 st1 4-18 status register 2 st2 4-19 ccu register ccu register C 6-19 ocem registers status 0 register C 8-4 status 1 register C 8-6 mode register C 8-7 data address breakpoint C 8-9 data address mask C 8-9 program address breakpoint counter 3 C 8-10 program address breakpoint counter 2 C 8-10 program address breakpoint counter 1 C 8-10 program address breakpoint 3 C 8-10 program address breakpoint 2 C 8-10 program address breakpoint 1 C 8-10 program flow trace register C 8-10 scanice register scan control register C 9-7 table a.1 CWDSP1650 registers (cont.) functional block register name abbreviations reference page (sheet 2 of 2)
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